Commit 7b97a200 authored by TheClams's avatar TheClams Committed by Will Bond

Add new package (Smart VHDL) (#6251)

* Move SystemVerilog repo to its github mirror

* Add new package (Smart VHDL)

Also add missing description for my other package (SystemVerilog)

* Update Sublime min version to 3092
parent 3edac351
...@@ -2086,6 +2086,19 @@ ...@@ -2086,6 +2086,19 @@
} }
] ]
}, },
{
"name": "Smart VHDL",
"description": "Syntax Highlighting, Snippets, code navigation and more for VHDL",
"details": "https://github.com/TheClams/SmartVHDL",
"issues": "https://bitbucket.org/Clams/smartvhdl/issues",
"labels": ["language syntax", "snippets"],
"releases": [
{
"sublime_text": ">=3092",
"tags": true
}
]
},
{ {
"details": "https://github.com/iiAtlas/SmartGoogle", "details": "https://github.com/iiAtlas/SmartGoogle",
"releases": [ "releases": [
...@@ -4996,6 +5009,7 @@ ...@@ -4996,6 +5009,7 @@
}, },
{ {
"name": "SystemVerilog", "name": "SystemVerilog",
"description": "Syntax Highlighting, smart snippets, autocompletion, code navigation and more for Verilog and SystemVerilog",
"details": "https://github.com/TheClams/SystemVerilog", "details": "https://github.com/TheClams/SystemVerilog",
"homepage": "http://sv-doc.readthedocs.org/en/latest", "homepage": "http://sv-doc.readthedocs.org/en/latest",
"issues": "https://bitbucket.org/Clams/sublimesystemverilog/issues", "issues": "https://bitbucket.org/Clams/sublimesystemverilog/issues",
......
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