sha instrumented code with power and manual instrumentation.

Signed-off-by: Gaurav Kukreja <gaurav@gauravk.in>

instrument/examples/sha/instrumented_power/Makefile

+include ../../../../cache_simulator/Makefile.macros
+include ../../../../branch_predictor/Makefile.macros
+include ../../../../power_estimator/Makefile.macros
+
+CC = gcc
+CFLAGS = -O2 -std=c99
+INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS) -I$(POWEREST_HEADERS)
+LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB) -L$(POWEREST_LIB)
+
+APP_SOURCES = my_mem_IR.c sha_driver_IR.c sha_IR.c
+
+all: sha.out
+
+sha.out: $(APP_SOURCES)
+	$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred -lpowerEst
+
+clean: 
+	rm -rf *.o sha.out
+	for f in $(SOURCES); do \
+		rm -rf $$f; \
+	done

instrument/examples/sha/instrumented_power/my_defines.h

+#ifndef __MY_DEFINES_H
+#define __MY_DEFINES_H
+
+#define ARR_SIZE 311824
+
+#endif

instrument/examples/sha/instrumented_power/my_mem.h

+#ifndef __MY_MEMCPY_H
+#define __MY_MEMCPY_H
+
+void* my_memcpy (void*dest, unsigned long dest_addr, const void*src, unsigned long src_addr, size_t count);
+void * my_memset (void *s, unsigned long s_addr, int c, size_t n);
+
+#endif

instrument/examples/sha/instrumented_power/my_mem_IR.c

+/***********************************************************
+ Intermediate representation of
+    sha/app_dir/my_mem.c
+
+ Converted by ir2c v0.1
+
+ ***********************************************************/
+#include <limits.h>
+#include <stdint.h>
+#include "ir2c.h"
+#include "cacheSim.h"
+#include "branchPred.h"
+#include "power_estimator.h"
+extern unsigned long SP;
+extern unsigned long long memAccessCycles;
+extern unsigned long long pipelineCycles;
+extern struct csim_result_t csim_result;
+
+/*
+Author - Suhas Chakravarty
+memcpy implementation taken from 
+www.danielvik.com/2010/02/fast-memcpy-in-c.html
+Renamed to my_memcpy
+Created - 17 Nov 2012
+Last modified - 17 Nov 2012
+*/
+
+#include <stdlib.h>
+
+
+void* my_memcpy (void*dest, unsigned long dest_addr, const void*src, unsigned long src_addr, size_t count) {
+  uintptr_t ivtmp_23;
+
+my_memcpybb_2:
+//  # PRED: ENTRY [100.0%]  (fallthru,exec)
+pipelineCycles += 2;
+enterBlock(0x748, 0x74c);
+memAccessCycles += simICache(0x748, 8, &csim_result); // GK
+SP = SP + 0x0;
+  if (count != 0)
+    goto my_memcpybb_5;
+  else
+    goto my_memcpybb_4;
+//  # SUCC: 5 [91.0%]  (true,exec) 4 [9.0%]  (false,exec)
+
+my_memcpybb_5:
+//  # PRED: 2 [91.0%]  (true,exec)
+  ivtmp_23 = 0;
+//  # SUCC: 3 [100.0%]  (fallthru)
+
+my_memcpybb_3:
+//  # PRED: 3 [91.0%]  (true,exec) 5 [100.0%]  (fallthru)
+  pipelineCycles += 17 - (enterBlock(0x750, 0x764) ? 7 : 0);
+  memAccessCycles += simICache(0x750, 24, &csim_result); // GK
+  memAccessCycles += simDCache(src_addr + ivtmp_23, 1, &csim_result); // GK
+  memAccessCycles += simDCache(dest_addr + ivtmp_23, 0, &csim_result); // GK 
+  *(char *)((uintptr_t)dest + (uintptr_t)ivtmp_23) = *(char *)((uintptr_t)src + (uintptr_t)ivtmp_23);
+  ivtmp_23 = ivtmp_23 + 1;
+  if (ivtmp_23 != count)
+    goto my_memcpybb_3;
+  else
+    goto my_memcpybb_4;
+//  # SUCC: 3 [91.0%]  (true,exec) 4 [9.0%]  (false,exec)
+
+my_memcpybb_4:
+  pipelineCycles += 8 - (enterBlock(0x768, 0x768) ? 7 : 0);
+//  # PRED: 3 [9.0%]  (false,exec) 2 [9.0%]  (false,exec)
+  return (uintptr_t)dest;
+//  # SUCC: EXIT [100.0%] 
+
+}
+
+
+
+void* my_memset (void *s, unsigned long s_addr, int c, size_t n) {
+  uintptr_t ivtmp_56;
+
+my_memsetbb_2:
+//  # PRED: ENTRY [100.0%]  (fallthru,exec)
+pipelineCycles += 2;
+enterBlock(0x76c, 0x770);
+memAccessCycles += simICache(0x76c, 8, &csim_result);
+SP = SP + 0x0;
+  if (n != 0)
+    goto my_memsetbb_5;
+  else
+    goto my_memsetbb_4;
+//  # SUCC: 5 [91.0%]  (true,exec) 4 [9.0%]  (false,exec)
+
+my_memsetbb_5:
+//  # PRED: 2 [91.0%]  (true,exec)
+  ivtmp_56 = 0;
+//  # SUCC: 3 [100.0%]  (fallthru)
+
+my_memsetbb_3:
+//  # PRED: 3 [91.0%]  (true,exec) 5 [100.0%]  (fallthru)
+pipelineCycles += 12 - (enterBlock(0x774, 0x784) ? 7 : 0);
+memAccessCycles += simICache(0x774, 20, &csim_result);
+memAccessCycles += simDCache(s_addr + ivtmp_56, 0, &csim_result);
+  *(char *)((uintptr_t)s + (uintptr_t)ivtmp_56) = (char) (char) c;
+  ivtmp_56 = ivtmp_56 + 1;
+  if (ivtmp_56 != n)
+    goto my_memsetbb_3;
+  else
+    goto my_memsetbb_4;
+//  # SUCC: 3 [91.0%]  (true,exec) 4 [9.0%]  (false,exec)
+
+my_memsetbb_4:
+//  # PRED: 3 [9.0%]  (false,exec) 2 [9.0%]  (false,exec)
+pipelineCycles += 8 - (enterBlock(0x788, 0x788) ? 7 : 0);
+  return (uintptr_t)s;
+//  # SUCC: EXIT [100.0%] 
+
+}
+
+

instrument/examples/sha/instrumented_power/my_variable.h

+unsigned int ARR_SIZE = 311824;
+unsigned long ARR_SIZE_addr = 0x55e28;
+//unsigned int ARR_SIZE = 3247553;

instrument/examples/sha/instrumented_power/sha.h

+#ifndef SHA_H
+#define SHA_H
+
+/* NIST Secure Hash Algorithm */
+/* heavily modified from Peter C. Gutmann's implementation */
+
+/* Useful defines & typedefs */
+
+typedef unsigned char BYTE;
+typedef unsigned long LONG;
+
+#define SHA_BLOCKSIZE		64
+#define SHA_DIGESTSIZE		20
+
+struct SHA_INFO {
+    unsigned long digest[5];		/* message digest */
+    unsigned long count_lo, count_hi;	/* 64-bit bit count */
+    unsigned long data[16];		/* SHA data buffer */
+};
+
+void  sha_init (struct SHA_INFO *sha_info, unsigned long sha_info_addr);
+void  sha_update (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsigned char *buffer, unsigned long buffer_addr, int count);
+void  sha_final (struct SHA_INFO *sha_info, unsigned long sha_info_addr);
+
+void  sha_stream (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsigned char *inData, unsigned long inData_addr, unsigned long int dSize);
+void  sha_print (struct SHA_INFO *sha_info, unsigned long sha_info_addr);
+
+#endif /* SHA_H */

instrument/examples/sha/instrumented_power/sha_driver_IR.c

+/***********************************************************
+ Intermediate representation of
+    sha/app_dir/sha_driver.c
+
+ Converted by ir2c v0.1
+
+ ***********************************************************/
+#include <limits.h>
+#include <stdint.h>
+#include "ir2c.h"
+#include "cacheSim.h"
+#include "branchPred.h"
+#include "power_estimator.h"
+unsigned long SP = 0x1234;
+unsigned long long memAccessCycles = 0;
+unsigned long long pipelineCycles = 0;
+struct csim_result_t csim_result;
+
+/* NIST Secure Hash Algorithm */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <time.h>
+#include "sha.h"
+#include "in_small.h"
+#include "my_variable.h"
+struct SHA_INFO sha_info; //making global
+unsigned long sha_info_addr = 0x56770;
+
+
+int main() {
+mainbb_2:
+//  # PRED: ENTRY [100.0%]  (fallthru,exec)
+cacheSimInit(&csim_result);
+branchPred_init();
+power_estimator_init();
+SP = SP + 0x8;
+memAccessCycles += simDCache(0x224, 1, &csim_result);  // PC Relative Load
+memAccessCycles += simDCache(0x228, 1, &csim_result);  // PC Relative Load
+memAccessCycles += simDCache(0x22c, 1, &csim_result);  // PC Relative Load
+// Simulating I Cache for obj block 0
+memAccessCycles += simICache(0x200, 36, &csim_result);
+estimate_power("mainbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
+// TODO: UnmappedLS: Load GlobalVar ARR_SIZE at line 154 -- Done
+memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result); // GK
+pipelineCycles += 16 - (enterBlock(0x96, 0x9e) ? 7 : 0);
+  sha_stream (&sha_info, sha_info_addr,  &in_Data, in_Data_addr,  ARR_SIZE);
+  printf("memAccessCycles = \%llu\n", memAccessCycles);
+  printf("pipelineCycles = \%llu\n", pipelineCycles);
+  cacheSimFini(&csim_result);
+  power_estimator_fini();
+  return 0;
+//  # SUCC: EXIT [100.0%] 
+
+}
+
+