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hostCompiledSimulation
Commit d126c154 authored by Gaurav Kukreja's avatar Gaurav Kukreja
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sha instrumented code with power and manual instrumentation. 

Signed-off-by: Gaurav Kukreja's avatarGaurav Kukreja <gaurav@gauravk.in>
parent b390b0a1
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instrument/examples/sha/instrumented_power/Makefile 0 → 100644
View file @ d126c154
include ../../../../cache_simulator/Makefile.macros
include ../../../../branch_predictor/Makefile.macros
include ../../../../power_estimator/Makefile.macros
CC = gcc
CFLAGS = -O2 -std=c99
INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS) -I$(POWEREST_HEADERS)
LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB) -L$(POWEREST_LIB)
APP_SOURCES = my_mem_IR.c sha_driver_IR.c sha_IR.c
all: sha.out
sha.out: $(APP_SOURCES)
$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred -lpowerEst
clean:
rm -rf *.o sha.out
for f in $(SOURCES); do \
rm -rf $$f; \
done
instrument/examples/sha/instrumented_power/\ 0 → 100644
View file @ d126c154
/***********************************************************
Intermediate representation of
sha/app_dir/sha.c
Converted by ir2c v0.1
***********************************************************/
#include <limits.h>
#include <stdint.h>
#include "ir2c.h"
#include "cacheSim.h"
#include "branchPred.h"
#include "power_estimator.h"
extern unsigned long SP;
extern unsigned long long memAccessCycles;
extern unsigned long long pipelineCycles;
extern struct csim_result_t csim_result;
/* NIST Secure Hash Algorithm */
/* heavily modified by Uwe Hollerbach uh@alumni.caltech edu */
/* from Peter C. Gutmann's implementation as found in */
/* Applied Cryptography by Bruce Schneier */
/* NIST's proposed modification to SHA of 7/11/94 may be */
/* activated by defining USE_MODIFIED_SHA */
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "sha.h"
#include "my_mem.h"
//#include "my_defines.h"
//#include "my_variable.h"
/* SHA f()-functions */
extern unsigned int ARR_SIZE;
unsigned long ARR_SIZE_addr = 0x55e28;
#define f1(x,y,z) ((x & y) | (~x & z))
#define f2(x,y,z) (x ^ y ^ z)
#define f3(x,y,z) ((x & y) | (x & z) | (y & z))
#define f4(x,y,z) (x ^ y ^ z)
/* SHA constants */
#define CONST1 0x5a827999L
#define CONST2 0x6ed9eba1L
#define CONST3 0x8f1bbcdcL
#define CONST4 0xca62c1d6L
/* 32-bit rotate */
#define ROT32(x,n) ((x << n) | (x >> (32 - n)))
#define FUNC(n,i) \
temp = ROT32(A,5) + f##n(B,C,D) + E + W[i] + CONST##n; \
E = D; D = C; C = ROT32(B,30); B = A; A = temp
/* do SHA transformation */
static void sha_transform (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
long unsigned int A_133;
long unsigned int E_132;
uintptr_t D_131;
long unsigned int B_130;
long unsigned int A_129;
long unsigned int E_128;
uintptr_t D_127;
long unsigned int B_126;
long unsigned int A_125;
long unsigned int E_124;
long unsigned int E_123;
uintptr_t D_122;
uintptr_t D_121;
long unsigned int B_120;
long unsigned int B_119;
long unsigned int A_118;
long unsigned int A_117;
uintptr_t ivtmp_116;
uintptr_t ivtmp_115;
long unsigned int C_114;
long unsigned int temp_113;
long unsigned int C_105;
long unsigned int temp_104;
long unsigned int C_101;
long unsigned int temp_100;
long unsigned int C_97;
uintptr_t ivtmp_94;
unsigned long ivtmp_94_addr;
uintptr_t ivtmp_93;
uintptr_t D_2940;
uintptr_t ivtmp_79;
uintptr_t ivtmp_71;
uintptr_t D_2917;
uintptr_t ivtmp_63;
long unsigned int W[80];
unsigned long W_addr = 0x10;
long unsigned int E;
long unsigned int D;
long unsigned int C;
long unsigned int B;
long unsigned int A;
long unsigned int temp;
sha_transformbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x170;
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x230, 20, &csim_result);
estimate_power("sha_transformbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0xa4, 0xa8) ? 7 : 0);
ivtmp_94 = (uintptr_t)sha_info;
ivtmp_94_addr = sha_indo_addr;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
ivtmp_93 = 0;
// # SUCC: 3 [100.0%] (fallthru,exec)
sha_transformbb_3:
// # PRED: 3 [94.1%] (true,exec) 2 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + W_addr + (+ivtmp_93)), 0, &csim_result);
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x244, 28, &csim_result);
memAccessCycles += simDCache(ivtmp_94_addr + 28, &csim_result);
estimate_power("sha_transformbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar sha_info at line 170
pipelineCycles += 12 - (enterBlock(0xa9, 0xaf) ? 7 : 0);
*(long unsigned int*)((uintptr_t)&W + (uintptr_t)ivtmp_93) = *(long unsigned int*)((uintptr_t)ivtmp_94 + 28);
ivtmp_93 = ivtmp_93 + 4;
ivtmp_94 = ivtmp_94 + 4;
ivtmp_94_addr = ivtmp_94_addr + 4;
if (ivtmp_93 != 64)
goto sha_transformbb_3;
else
goto sha_transformbb_4;
// # SUCC: 3 [94.1%] (true,exec) 4 [5.9%] (false,exec)
sha_transformbb_4:
// # PRED: 3 [5.9%] (false,exec)
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x260, 8, &csim_result);
estimate_power("sha_transformbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0xb0, 0xb1) ? 7 : 0);
ivtmp_79 = (uintptr_t)&W[13];
ivtmp_63 = (uintptr_t)&W;
D_2940 = ivtmp_63 + 308;
// # SUCC: 5 [100.0%] (fallthru,exec)
sha_transformbb_5:
// # PRED: 5 [98.5%] (true,exec) 4 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x268, 44, &csim_result);
estimate_power("sha_transformbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 178
// TODO: UnmappedLS: Load LocalVar W at line 179
// TODO: UnmappedLS: Load LocalVar W at line 181
// TODO: UnmappedLS: Load LocalVar W at line 183
// TODO: UnmappedLS: Store LocalVar W at line 185
pipelineCycles += 23 - (enterBlock(0xb2, 0xbc) ? 7 : 0);
*(long unsigned int*)((uintptr_t)ivtmp_79 + 12) = ((*(long unsigned int*)((uintptr_t)ivtmp_79 + (int)4294967276) ^ *(long unsigned int*)((uintptr_t)ivtmp_79)) ^ *(long unsigned int*)((uintptr_t)ivtmp_79 + (int)4294967252)) ^ *(long unsigned int*)((uintptr_t)ivtmp_79 + (int)4294967244);
ivtmp_79 = ivtmp_79 + 4;
if (ivtmp_79 != D_2940)
goto sha_transformbb_5;
else
goto sha_transformbb_6;
// # SUCC: 5 [98.5%] (true,exec) 6 [1.5%] (false,exec)
sha_transformbb_6:
// # PRED: 5 [1.5%] (false,exec)
memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache((SP + 0x8), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache((SP + 0x0), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x8), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache(0x460, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 4
memAccessCycles += simICache(0x294, 68, &csim_result);
estimate_power("sha_transformbb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar sha_info at line 189
// TODO: UnmappedLS: Load GlobalVar sha_info at line 190
// TODO: UnmappedLS: Load GlobalVar sha_info at line 192
// TODO: UnmappedLS: Load GlobalVar sha_info at line 194
// TODO: UnmappedLS: Load GlobalVar sha_info at line 196
pipelineCycles += 24 - (enterBlock(0xbd, 0xcd) ? 7 : 0);
A = sha_info->digest[0];
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
B = sha_info->digest[1];
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
C = sha_info->digest[2];
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
D = sha_info->digest[3];
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
E = sha_info->digest[4];
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
A_133 = A;
ivtmp_71 = 0;
// # SUCC: 7 [100.0%] (fallthru,exec)
sha_transformbb_7:
// # PRED: 13 [100.0%] (fallthru) 6 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 5
memAccessCycles += simICache(0x2d8, 48, &csim_result);
estimate_power("sha_transformbb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 206
pipelineCycles += 16 - (enterBlock(0xce, 0xd9) ? 7 : 0);
temp = (((*(long unsigned int*)((uintptr_t)&W + (uintptr_t)ivtmp_71) + 1518500249) + E) + ((A_133<<27)|(A_133>>(sizeof(A_133)*CHAR_BIT-27)))) + (~B & D | C & B);
C_97 = (B<<2)|(B>>(sizeof(B)*CHAR_BIT-2));
ivtmp_71 = ivtmp_71 + 4;
if (ivtmp_71 != 80)
goto sha_transformbb_13;
else
goto sha_transformbb_8;
// # SUCC: 13 [95.2%] (true,exec) 8 [4.8%] (false,exec)
sha_transformbb_13:
// # PRED: 7 [95.2%] (true,exec)
// Simulating I Cache for obj block 6
memAccessCycles += simICache(0x308, 24, &csim_result);
estimate_power("sha_transformbb_13", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0xda, 0xdf) ? 7 : 0);
E = D;
D = C;
C = C_97;
B = A_133;
A_133 = temp;
goto sha_transformbb_7;
// # SUCC: 7 [100.0%] (fallthru)
sha_transformbb_8:
// # PRED: 7 [4.8%] (false,exec)
memAccessCycles += simDCache(0x464, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 7
memAccessCycles += simICache(0x320, 16, &csim_result);
estimate_power("sha_transformbb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0xe0, 0xe3) ? 7 : 0);
D_2917 = ivtmp_63 + 80;
ivtmp_116 = ivtmp_63;
E_132 = D;
D_131 = C;
B_130 = A_133;
A_129 = temp;
// # SUCC: 9 [100.0%] (fallthru,exec)
sha_transformbb_9:
// # PRED: 14 [100.0%] (fallthru) 8 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 8
memAccessCycles += simICache(0x330, 44, &csim_result);
estimate_power("sha_transformbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 228
pipelineCycles += 17 - (enterBlock(0xe4, 0xee) ? 7 : 0);
temp_100 = (((*(long unsigned int*)((uintptr_t)ivtmp_116 + 80) + 1859775393) + E_132) + ((A_129<<27)|(A_129>>(sizeof(A_129)*CHAR_BIT-27)))) + ((C_97 ^ B_130) ^ D_131);
C_101 = (B_130<<2)|(B_130>>(sizeof(B_130)*CHAR_BIT-2));
ivtmp_116 = ivtmp_116 + 4;
if (ivtmp_116 != D_2917)
goto sha_transformbb_14;
else
goto sha_transformbb_16;
// # SUCC: 14 [95.2%] (true,exec) 16 [4.8%] (false,exec)
sha_transformbb_16:
// # PRED: 9 [4.8%] (false,exec)
memAccessCycles += simDCache(0x468, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 10
memAccessCycles += simICache(0x374, 16, &csim_result);
estimate_power("sha_transformbb_16", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0xf5, 0xf8) ? 7 : 0);
ivtmp_115 = ivtmp_63;
E_128 = D_131;
D_127 = C_97;
B_126 = A_129;
A_125 = temp_100;
goto sha_transformbb_10;
// # SUCC: 10 [100.0%] (fallthru)
sha_transformbb_14:
// # PRED: 9 [95.2%] (true,exec)
// Simulating I Cache for obj block 9
memAccessCycles += simICache(0x35c, 24, &csim_result);
estimate_power("sha_transformbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0xef, 0xf4) ? 7 : 0);
E_132 = D_131;
D_131 = C_97;
C_97 = C_101;
B_130 = A_129;
A_129 = temp_100;
goto sha_transformbb_9;
// # SUCC: 9 [100.0%] (fallthru)
sha_transformbb_15:
// # PRED: 10 [95.2%] (true,exec)
// Simulating I Cache for obj block 12
memAccessCycles += simICache(0x3b8, 24, &csim_result);
estimate_power("sha_transformbb_15", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0x106, 0x10b) ? 7 : 0);
E_128 = D_127;
D_127 = C_101;
C_101 = C_105;
B_126 = A_125;
A_125 = temp_104;
// # SUCC: 10 [100.0%] (fallthru)
sha_transformbb_10:
// # PRED: 15 [100.0%] (fallthru) 16 [100.0%] (fallthru)
// Simulating I Cache for obj block 11
memAccessCycles += simICache(0x384, 52, &csim_result);
estimate_power("sha_transformbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 249
pipelineCycles += 18 - (enterBlock(0xf9, 0x105) ? 7 : 0);
temp_104 = (((*(long unsigned int*)((uintptr_t)ivtmp_115 + 160) + (int)2400959708) + E_128) + ((A_125<<27)|(A_125>>(sizeof(A_125)*CHAR_BIT-27)))) + ((D_127 | C_101) & B_126 | D_127 & C_101);
C_105 = (B_126<<2)|(B_126>>(sizeof(B_126)*CHAR_BIT-2));
ivtmp_115 = ivtmp_115 + 4;
if (ivtmp_115 != D_2917)
goto sha_transformbb_15;
else
goto sha_transformbb_18;
// # SUCC: 15 [95.2%] (true,exec) 18 [4.8%] (false,exec)
sha_transformbb_18:
// # PRED: 10 [4.8%] (false,exec)
memAccessCycles += simDCache(0x46c, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 13
memAccessCycles += simICache(0x3d0, 8, &csim_result);
estimate_power("sha_transformbb_18", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0x10c, 0x10d) ? 7 : 0);
E_123 = D_127;
D_121 = C_101;
B_119 = A_125;
A_117 = temp_104;
// # SUCC: 11 [100.0%] (fallthru)
sha_transformbb_11:
// # PRED: 17 [100.0%] (fallthru) 18 [100.0%] (fallthru)
// Simulating I Cache for obj block 14
memAccessCycles += simICache(0x3d8, 44, &csim_result);
estimate_power("sha_transformbb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 270
pipelineCycles += 17 - (enterBlock(0x10e, 0x118) ? 7 : 0);
temp_113 = (((*(long unsigned int*)((uintptr_t)ivtmp_63 + 240) + (int)3395469782) + E_123) + ((A_117<<27)|(A_117>>(sizeof(A_117)*CHAR_BIT-27)))) + ((C_105 ^ B_119) ^ D_121);
C_114 = (B_119<<2)|(B_119>>(sizeof(B_119)*CHAR_BIT-2));
ivtmp_63 = ivtmp_63 + 4;
if (ivtmp_63 != D_2917)
goto sha_transformbb_17;
else
goto sha_transformbb_19;
// # SUCC: 17 [95.2%] (true,exec) 19 [4.8%] (false,exec)
sha_transformbb_17:
// # PRED: 11 [95.2%] (true,exec)
// Simulating I Cache for obj block 15
memAccessCycles += simICache(0x404, 24, &csim_result);
estimate_power("sha_transformbb_17", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0x119, 0x11e) ? 7 : 0);
E_123 = D_121;
D_121 = C_105;
C_105 = C_114;
B_119 = A_117;
A_117 = temp_113;
goto sha_transformbb_11;
// # SUCC: 11 [100.0%] (fallthru)
sha_transformbb_19:
// # PRED: 11 [4.8%] (false,exec)
memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x8), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x0), 1, &csim_result); // Reading Spilt Register
pipelineCycles += 34 - (enterBlock(0x11f, 0x12f) ? 7 : 0);
E_124 = D_121;
D_122 = C_105;
B_120 = A_117;
A_118 = temp_113;
// # SUCC: 12 [100.0%] (fallthru)
sha_transformbb_12:
// # PRED: 19 [100.0%] (fallthru)
// Simulating I Cache for obj block 16
memAccessCycles += simICache(0x41c, 68, &csim_result);
estimate_power("sha_transformbb_12", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Store GlobalVar sha_info at line 288
// TODO: UnmappedLS: Store GlobalVar sha_info at line 291
// TODO: UnmappedLS: Store GlobalVar sha_info at line 294
// TODO: UnmappedLS: Store GlobalVar sha_info at line 297
// TODO: UnmappedLS: Store GlobalVar sha_info at line 300
sha_info->digest[0] = A_118 + A;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->digest[1] = B_120 + sha_info->digest[1];
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->digest[2] = C_114 + sha_info->digest[2];
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->digest[3] = D_122 + sha_info->digest[3];
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->digest[4] = E_124 + sha_info->digest[4];
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
return;
// # SUCC: EXIT [100.0%]
}
void sha_init (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
sha_initbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x0;
memAccessCycles += simDCache(0x4b4, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x4b8, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x4bc, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x4c0, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x470, 68, &csim_result);
estimate_power("sha_initbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Store GlobalVar sha_info at line 311
// TODO: UnmappedLS: Store GlobalVar sha_info at line 316
// TODO: UnmappedLS: Store GlobalVar sha_info at line 318
// TODO: UnmappedLS: Store GlobalVar sha_info at line 320
// TODO: UnmappedLS: Store GlobalVar sha_info at line 322
// TODO: UnmappedLS: Store GlobalVar sha_info at line 324
// TODO: UnmappedLS: Store GlobalVar sha_info at line 325
pipelineCycles += 23 - (enterBlock(0x136, 0x146) ? 7 : 0);
sha_info->digest[0] = 1732584193;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->digest[1] = 4023233417;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->digest[2] = 2562383102;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->digest[3] = 271733878;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->digest[4] = 3285377520;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->count_lo = 0;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->count_hi = 0;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
return;
// # SUCC: EXIT [100.0%]
}
void sha_print (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
sha_printbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x10;
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x718, 44, &csim_result);
estimate_power("sha_printbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 16 - (enterBlock(0x1e8, 0x1f2) ? 7 : 0);
printf (&"%08lx %08lx %08lx %08lx %08lx\n"[0], sha_info->digest[0], sha_info->digest[1], sha_info->digest[2], sha_info->digest[3], sha_info->digest[4]);
return;
// # SUCC: EXIT [100.0%]
}
void sha_final (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
int count_203;
long unsigned int hi_bit_count;
long unsigned int lo_bit_count;
int count;
long unsigned int * D_2805;
sha_finalbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x18;
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x58c, 60, &csim_result);
estimate_power("sha_finalbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Store GlobalVar sha_info at line 393
pipelineCycles += 23 - (enterBlock(0x181, 0x18f) ? 7 : 0);
lo_bit_count = sha_info->count_lo;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
hi_bit_count = sha_info->count_hi;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
count = (int) (lo_bit_count >> 3) & 63;
D_2805 = &sha_info->data;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
*(unsigned char*)( (uintptr_t)D_2805 + (unsigned int) count) = 128;
count_203 = count + 1;
if (count_203 > 56)
goto sha_finalbb_3;
else
goto sha_finalbb_4;
// # SUCC: 3 [39.0%] (true,exec) 4 [61.0%] (false,exec)
sha_finalbb_3:
// # PRED: 2 [39.0%] (true,exec)
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x5ec, 8, &csim_result);
estimate_power("sha_finalbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 8 - (enterBlock(0x199, 0x19a) ? 7 : 0);
my_memset (D_2805 + (unsigned int) count_203, D_2805_addr, 0, (size_t) (64 - count_203));
sha_transform (sha_info, sha_info_addr);
my_memset (D_2805, D_2805_addr, 0, 56);
goto sha_finalbb_5;
// # SUCC: 5 [100.0%] (fallthru,exec)
sha_finalbb_4:
// # PRED: 2 [61.0%] (false,exec)
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x5c8, 36, &csim_result);
estimate_power("sha_finalbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0x190, 0x198) ? 7 : 0);
my_memset (D_2805 + (unsigned int) count_203, D_2805_addr, 0, (size_t) (56 - count_203));
// # SUCC: 5 [100.0%] (fallthru,exec)
sha_finalbb_5:
// # PRED: 3 [100.0%] (fallthru,exec) 4 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x5f4, 24, &csim_result);
estimate_power("sha_finalbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Store GlobalVar sha_info at line 411
// TODO: UnmappedLS: Store GlobalVar sha_info at line 412
pipelineCycles += 16 - (enterBlock(0x19b, 0x1a0) ? 7 : 0);
sha_info->data[14] = hi_bit_count;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->data[15] = lo_bit_count;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_transform (sha_info, sha_info_addr);
return;
// # SUCC: EXIT [100.0%]
}
void sha_update (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsigned char *buffer, unsigned long buffer_addr, int count) {
uintptr_t D_3103;
uintptr_t ivtmp_232;
int D_3089;
uintptr_t D_3086;
long unsigned int * D_2795;
long unsigned int D_2787;
long unsigned int count_1;
long unsigned int D_2785;
sha_updatebb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x30;
pipelineCycles += 32 - (enterBlock(0x14d, 0x160) ? 7 : 0);
D_2785 = sha_info->count_lo;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
count_1 = (long unsigned int) count;
D_2787 = count_1 << 3;
if (D_2785 > D_2787 + D_2785)
goto sha_updatebb_3;
else
goto sha_updatebb_4;
// # SUCC: 3 [50.0%] (true,exec) 4 [50.0%] (false,exec)
sha_updatebb_3:
// # PRED: 2 [50.0%] (true,exec)
sha_info->count_hi = sha_info->count_hi + 1;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
// # SUCC: 4 [100.0%] (fallthru,exec)
sha_updatebb_4:
// # PRED: 2 [50.0%] (false,exec) 3 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x4c4, 80, &csim_result);
estimate_power("sha_updatebb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar sha_info at line 338
// TODO: UnmappedLS: Load GlobalVar sha_info at line 342
// TODO: UnmappedLS: Store GlobalVar sha_info at line 344
// TODO: UnmappedLS: Load GlobalVar sha_info at line 345
// TODO: UnmappedLS: Store GlobalVar sha_info at line 347
// TODO: UnmappedLS: Load GlobalVar sha_info at line 348
// TODO: UnmappedLS: Store GlobalVar sha_info at line 350
sha_info->count_lo = D_2787 + sha_info->count_lo;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->count_hi = (count_1 >> 29) + sha_info->count_hi;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
if (count > 63)
goto sha_updatebb_5;
else
goto sha_updatebb_8;
// # SUCC: 5 [91.0%] (true,exec) 8 [9.0%] (false,exec)
sha_updatebb_5:
// # PRED: 4 [91.0%] (true,exec)
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x514, 16, &csim_result);
estimate_power("sha_updatebb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0x161, 0x164) ? 7 : 0);
D_2795 = &sha_info->data;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
ivtmp_232 = 0;
// # SUCC: 6 [100.0%] (fallthru,exec)
sha_updatebb_6:
// # PRED: 6 [91.0%] (true,exec) 5 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Spilling Register
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x524, 44, &csim_result);
estimate_power("sha_updatebb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0x165, 0x16f) ? 7 : 0);
D_3103 = ivtmp_232 + (uintptr_t)buffer;
memAccessCycles += simDCache(buffer_addr, 1, &csim_result);
my_memcpy (D_2795, D_2795_addr, D_3103, D_3103_addr, 64);
sha_transform (sha_info, sha_info_addr);
ivtmp_232 = ivtmp_232 + 64;
if ((int) (count_1 - ivtmp_232) > 63)
goto sha_updatebb_6;
else
goto sha_updatebb_7;
// # SUCC: 6 [91.0%] (true,exec) 7 [9.0%] (false,exec)
sha_updatebb_7:
// # PRED: 6 [9.0%] (false,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x550, 32, &csim_result);
estimate_power("sha_updatebb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0x170, 0x177) ? 7 : 0);
D_3086 = (count_1 + (int)4294967232) / 64;
buffer = (uintptr_t)buffer + (D_3086 + 1) * 64;
memAccessCycles += simDCache(buffer_addr, 0, &csim_result);
D_3089 = count + -64;
count = D_3089 + (int) D_3086 * -64;
// # SUCC: 8 [100.0%] (fallthru,exec)
sha_updatebb_8:
// # PRED: 7 [100.0%] (fallthru,exec) 4 [9.0%] (false,exec)
// Simulating I Cache for obj block 4
memAccessCycles += simICache(0x570, 28, &csim_result);
estimate_power("sha_updatebb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 20 - (enterBlock(0x178, 0x17e) ? 7 : 0);
my_memcpy (&sha_info->data, sha_info_addr, buffer, buffer_addr, (size_t) count);
return;
// # SUCC: EXIT [100.0%]
}
void sha_stream (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsigned char *inData, unsigned long inData_addr, unsigned long int dSize) {
long unsigned int end_289;
long unsigned int end_288;
uintptr_t ivtmp_273;
uintptr_t D_3143;
uintptr_t ivtmp_267;
unsigned char data[8192];
long unsigned int count;
long unsigned int end;
long unsigned int start;
long unsigned int j;
unsigned int ARR_SIZE_4;
sha_streambb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x2030;
memAccessCycles += simDCache(0x714, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x60c, 48, &csim_result);
estimate_power("sha_streambb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 23 - (enterBlock(0x1a3, 0x1ae) ? 7 : 0);
ARR_SIZE_4 = ARR_SIZE;
j = ARR_SIZE_4 / 8192;
sha_init (sha_info, sha_info_addr);
if (j != 0)
goto sha_streambb_13;
else
goto sha_streambb_6;
// # SUCC: 13 [91.0%] (true,exec) 6 [9.0%] (false,exec)
sha_streambb_13:
// # PRED: 2 [91.0%] (true,exec)
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x63c, 36, &csim_result);
estimate_power("sha_streambb_13", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0x1af, 0x1b7) ? 7 : 0);
end_289 = 0;
count = 0;
// # SUCC: 3 [100.0%] (fallthru)
sha_streambb_3:
// # PRED: 12 [100.0%] (fallthru) 13 [100.0%] (fallthru)
pipelineCycles += 9 - (enterBlock(0x1b8, 0x1ba) ? 7 : 0);
end_288 = end_289 + 8192;
if (end_288 > end_289)
goto sha_streambb_14;
else
goto sha_streambb_5;
// # SUCC: 14 [99.0%] (true,exec) 5 [1.0%] (false,exec)
sha_streambb_14:
// # PRED: 3 [99.0%] (true,exec)
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x66c, 4, &csim_result);
estimate_power("sha_streambb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 8 - (enterBlock(0x1bb, 0x1bb) ? 7 : 0);
ivtmp_273 = 0;
// # SUCC: 4 [100.0%] (fallthru)
sha_streambb_4:
// # PRED: 4 [99.0%] (true,exec) 14 [100.0%] (fallthru)
// Simulating I Cache for obj block 4
memAccessCycles += simICache(0x670, 24, &csim_result);
estimate_power("sha_streambb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar in_Data at line 445
// TODO: UnmappedLS: Inaccurately Matched Store at line 446
pipelineCycles += 11 - (enterBlock(0x1bc, 0x1c1) ? 7 : 0);
*(unsigned char*)((uintptr_t)&data + (uintptr_t)ivtmp_273) = *(unsigned char *)((unsigned char *) (end_289 + (uintptr_t)inData) + (uintptr_t)ivtmp_273);
ivtmp_273 = ivtmp_273 + 1;
if (ivtmp_273 != 8192)
goto sha_streambb_4;
else
goto sha_streambb_5;
// # SUCC: 4 [99.0%] (true,exec) 5 [1.0%] (false,exec)
sha_streambb_5:
// # PRED: 4 [1.0%] (false,exec) 3 [1.0%] (false,exec)
// Simulating I Cache for obj block 5
memAccessCycles += simICache(0x688, 32, &csim_result);
estimate_power("sha_streambb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0x1c2, 0x1c9) ? 7 : 0);
sha_update (sha_info, sha_info_addr, &data, data_addr, 8192);
count = count + 1;
if (j > count)
goto sha_streambb_12;
else
goto sha_streambb_6;
// # SUCC: 12 [91.0%] (true,exec) 6 [9.0%] (false,exec)
sha_streambb_12:
// # PRED: 5 [91.0%] (true,exec)
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x660, 12, &csim_result);
estimate_power("sha_streambb_12", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
end_289 = end_288;
goto sha_streambb_3;
// # SUCC: 3 [100.0%] (fallthru)
sha_streambb_6:
// # PRED: 5 [9.0%] (false,exec) 2 [9.0%] (false,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
// Simulating I Cache for obj block 6
memAccessCycles += simICache(0x6a8, 12, &csim_result);
estimate_power("sha_streambb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0x1ca, 0x1cc) ? 7 : 0);
if (ARR_SIZE_4 & 8191 != 0)
goto sha_streambb_7;
else
goto sha_streambb_11;
// # SUCC: 7 [61.0%] (true,exec) 11 [39.0%] (false,exec)
sha_streambb_7:
// # PRED: 6 [61.0%] (true,exec)
memAccessCycles += simDCache(0x714, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 7
memAccessCycles += simICache(0x6b4, 20, &csim_result);
estimate_power("sha_streambb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0x1cd, 0x1d1) ? 7 : 0);
start = j * 8192;
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
end = ARR_SIZE;
if (start < end)
goto sha_streambb_8;
else
goto sha_streambb_10;
// # SUCC: 8 [99.0%] (true,exec) 10 [1.0%] (false,exec)
sha_streambb_8:
// # PRED: 7 [99.0%] (true,exec)
// Simulating I Cache for obj block 8
memAccessCycles += simICache(0x6c8, 16, &csim_result);
estimate_power("sha_streambb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0x1d2, 0x1d5) ? 7 : 0);
D_3143 = end - start;
ivtmp_267 = 0;
// # SUCC: 9 [100.0%] (fallthru,exec)
sha_streambb_9:
// # PRED: 9 [99.0%] (true,exec) 8 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + 0x8), 1, &csim_result); // Spilling Register
// Simulating I Cache for obj block 9
memAccessCycles += simICache(0x6d8, 20, &csim_result);
estimate_power("sha_streambb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar in_Data at line 470
pipelineCycles += 11 - (enterBlock(0x1d6, 0x1da) ? 7 : 0);
*(unsigned char*)((uintptr_t)&data + (uintptr_t)ivtmp_267) = *(unsigned char *)((uintptr_t)inData + start + (uintptr_t)ivtmp_267);
memAccessCycles += simDCache(inData_addr + (+start+ivtmp_267), 1, &csim_result);
ivtmp_267 = ivtmp_267 + 1;
if (ivtmp_267 != D_3143)
goto sha_streambb_9;
else
goto sha_streambb_10;
// # SUCC: 9 [99.0%] (true,exec) 10 [1.0%] (false,exec)
sha_streambb_10:
// # PRED: 9 [1.0%] (false,exec) 7 [1.0%] (false,exec)
// Simulating I Cache for obj block 10
memAccessCycles += simICache(0x6ec, 16, &csim_result);
estimate_power("sha_streambb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 10 - (enterBlock(0x1db, 0x1de) ? 7 : 0);
sha_update (sha_info, sha_info_addr, &data, data_addr, (int) (end - start));
// # SUCC: 11 [100.0%] (fallthru,exec)
sha_streambb_11:
// # PRED: 6 [39.0%] (false,exec) 10 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 11
memAccessCycles += simICache(0x6fc, 24, &csim_result);
estimate_power("sha_streambb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0x1df, 0x1e4) ? 7 : 0);
sha_final (sha_info, sha_info_addr);
return;
// # SUCC: EXIT [100.0%]
}
instrument/examples/sha/instrumented_power/in_small.h 0 → 100644
View file @ d126c154
This source diff could not be displayed because it is too large. You can view the blob instead.
instrument/examples/sha/instrumented_power/my_defines.h 0 → 100644
View file @ d126c154
#ifndef __MY_DEFINES_H
#define __MY_DEFINES_H
#define ARR_SIZE 311824
#endif
instrument/examples/sha/instrumented_power/my_mem.h 0 → 100644
View file @ d126c154
#ifndef __MY_MEMCPY_H
#define __MY_MEMCPY_H
void* my_memcpy (void*dest, unsigned long dest_addr, const void*src, unsigned long src_addr, size_t count);
void * my_memset (void *s, unsigned long s_addr, int c, size_t n);
#endif
instrument/examples/sha/instrumented_power/my_mem_IR.c 0 → 100644
View file @ d126c154
/***********************************************************
Intermediate representation of
sha/app_dir/my_mem.c
Converted by ir2c v0.1
***********************************************************/
#include <limits.h>
#include <stdint.h>
#include "ir2c.h"
#include "cacheSim.h"
#include "branchPred.h"
#include "power_estimator.h"
extern unsigned long SP;
extern unsigned long long memAccessCycles;
extern unsigned long long pipelineCycles;
extern struct csim_result_t csim_result;
/*
Author - Suhas Chakravarty
memcpy implementation taken from
www.danielvik.com/2010/02/fast-memcpy-in-c.html
Renamed to my_memcpy
Created - 17 Nov 2012
Last modified - 17 Nov 2012
*/
#include <stdlib.h>
void* my_memcpy (void*dest, unsigned long dest_addr, const void*src, unsigned long src_addr, size_t count) {
uintptr_t ivtmp_23;
my_memcpybb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
pipelineCycles += 2;
enterBlock(0x748, 0x74c);
memAccessCycles += simICache(0x748, 8, &csim_result); // GK
SP = SP + 0x0;
if (count != 0)
goto my_memcpybb_5;
else
goto my_memcpybb_4;
// # SUCC: 5 [91.0%] (true,exec) 4 [9.0%] (false,exec)
my_memcpybb_5:
// # PRED: 2 [91.0%] (true,exec)
ivtmp_23 = 0;
// # SUCC: 3 [100.0%] (fallthru)
my_memcpybb_3:
// # PRED: 3 [91.0%] (true,exec) 5 [100.0%] (fallthru)
pipelineCycles += 17 - (enterBlock(0x750, 0x764) ? 7 : 0);
memAccessCycles += simICache(0x750, 24, &csim_result); // GK
memAccessCycles += simDCache(src_addr + ivtmp_23, 1, &csim_result); // GK
memAccessCycles += simDCache(dest_addr + ivtmp_23, 0, &csim_result); // GK
*(char *)((uintptr_t)dest + (uintptr_t)ivtmp_23) = *(char *)((uintptr_t)src + (uintptr_t)ivtmp_23);
ivtmp_23 = ivtmp_23 + 1;
if (ivtmp_23 != count)
goto my_memcpybb_3;
else
goto my_memcpybb_4;
// # SUCC: 3 [91.0%] (true,exec) 4 [9.0%] (false,exec)
my_memcpybb_4:
pipelineCycles += 8 - (enterBlock(0x768, 0x768) ? 7 : 0);
// # PRED: 3 [9.0%] (false,exec) 2 [9.0%] (false,exec)
return (uintptr_t)dest;
// # SUCC: EXIT [100.0%]
}
void* my_memset (void *s, unsigned long s_addr, int c, size_t n) {
uintptr_t ivtmp_56;
my_memsetbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
pipelineCycles += 2;
enterBlock(0x76c, 0x770);
memAccessCycles += simICache(0x76c, 8, &csim_result);
SP = SP + 0x0;
if (n != 0)
goto my_memsetbb_5;
else
goto my_memsetbb_4;
// # SUCC: 5 [91.0%] (true,exec) 4 [9.0%] (false,exec)
my_memsetbb_5:
// # PRED: 2 [91.0%] (true,exec)
ivtmp_56 = 0;
// # SUCC: 3 [100.0%] (fallthru)
my_memsetbb_3:
// # PRED: 3 [91.0%] (true,exec) 5 [100.0%] (fallthru)
pipelineCycles += 12 - (enterBlock(0x774, 0x784) ? 7 : 0);
memAccessCycles += simICache(0x774, 20, &csim_result);
memAccessCycles += simDCache(s_addr + ivtmp_56, 0, &csim_result);
*(char *)((uintptr_t)s + (uintptr_t)ivtmp_56) = (char) (char) c;
ivtmp_56 = ivtmp_56 + 1;
if (ivtmp_56 != n)
goto my_memsetbb_3;
else
goto my_memsetbb_4;
// # SUCC: 3 [91.0%] (true,exec) 4 [9.0%] (false,exec)
my_memsetbb_4:
// # PRED: 3 [9.0%] (false,exec) 2 [9.0%] (false,exec)
pipelineCycles += 8 - (enterBlock(0x788, 0x788) ? 7 : 0);
return (uintptr_t)s;
// # SUCC: EXIT [100.0%]
}
instrument/examples/sha/instrumented_power/my_variable.h 0 → 100644
View file @ d126c154
unsigned int ARR_SIZE = 311824;
unsigned long ARR_SIZE_addr = 0x55e28;
//unsigned int ARR_SIZE = 3247553;
instrument/examples/sha/instrumented_power/power_trace.dat 0 → 100644
View file @ d126c154
sha_streambb_4, 10005, 108.942465
sha_streambb_4, 20007, 108.150556
sha_streambb_4, 30009, 107.701716
sha_streambb_4, 40011, 107.701716
sha_streambb_4, 50013, 107.701716
sha_transformbb_14, 60015, 101.260948
sha_transformbb_11, 70026, 89.261454
sha_transformbb_3, 80159, 89.404829
sha_transformbb_5, 90172, 89.180376
sha_transformbb_9, 100185, 89.264266
sha_transformbb_10, 110190, 89.271479
sha_transformbb_3, 120641, 89.416990
sha_transformbb_5, 130654, 89.180376
sha_transformbb_9, 140667, 89.264266
sha_transformbb_10, 150673, 89.581580
sha_transformbb_11, 160684, 91.704788
sha_transformbb_3, 170934, 92.628090
sha_transformbb_5, 180940, 91.735667
sha_transformbb_13, 190955, 91.602393
sha_transformbb_9, 200963, 91.679511
sha_transformbb_15, 210973, 91.714294
sha_transformbb_10, 220974, 91.622050
sha_transformbb_11, 230981, 91.709240
sha_transformbb_3, 241167, 92.645746
sha_transformbb_5, 251173, 91.735667
sha_transformbb_7, 261238, 91.914584
sha_transformbb_14, 271247, 91.693276
sha_transformbb_10, 281262, 91.620324
sha_transformbb_10, 291276, 91.682208
sha_transformbb_11, 301283, 91.709240
sha_transformbb_3, 311469, 92.645746
sha_transformbb_5, 321475, 91.735667
sha_transformbb_13, 331490, 91.602393
sha_transformbb_9, 341498, 91.679511
sha_transformbb_15, 351508, 91.714294
sha_transformbb_10, 361509, 91.622050
sha_transformbb_11, 371516, 91.709240
sha_transformbb_3, 381702, 92.645746
sha_transformbb_5, 391708, 91.735667
sha_transformbb_7, 401773, 91.914584
sha_transformbb_14, 411782, 91.693276
sha_transformbb_10, 421797, 91.620324
sha_transformbb_10, 431811, 91.682208
sha_transformbb_11, 441818, 91.709240
sha_transformbb_3, 452004, 92.645746
sha_transformbb_5, 462010, 91.735667
sha_transformbb_13, 472025, 91.602393
sha_transformbb_9, 482033, 91.679511
sha_transformbb_15, 492043, 91.714294
sha_transformbb_10, 502044, 91.622050
sha_transformbb_11, 512051, 91.709240
sha_transformbb_3, 522237, 92.645746
sha_transformbb_5, 532243, 91.735667
sha_transformbb_7, 542308, 91.914584
sha_transformbb_14, 552317, 91.693276
sha_transformbb_10, 562332, 91.620324
sha_transformbb_10, 572346, 91.682208
sha_transformbb_11, 582353, 91.709240
sha_transformbb_3, 592539, 92.645746
sha_transformbb_5, 602545, 91.735667
sha_transformbb_13, 612560, 91.602393
sha_transformbb_9, 622568, 91.679511
sha_transformbb_15, 632578, 91.714294
sha_transformbb_10, 642579, 91.622050
sha_streambb_4, 652584, 97.286049
sha_streambb_4, 662586, 107.701716
sha_streambb_4, 672588, 107.701716
sha_streambb_4, 682592, 107.678418
sha_streambb_4, 692594, 107.701716
sha_transformbb_3, 702939, 98.250075
sha_transformbb_5, 712943, 89.171053
sha_transformbb_14, 722957, 89.287533
sha_transformbb_17, 732962, 89.276118
sha_transformbb_3, 743295, 89.367862
sha_transformbb_5, 753299, 89.171053
sha_transformbb_14, 763313, 89.287533
sha_transformbb_17, 773318, 89.276118
sha_transformbb_3, 783651, 89.367862
sha_transformbb_5, 793655, 89.619804
sha_transformbb_7, 803666, 91.645214
sha_transformbb_16, 813680, 91.703019
sha_transformbb_10, 823685, 91.622268
sha_updatebb_6, 833732, 91.595935
sha_transformbb_3, 843808, 92.767257
sha_transformbb_5, 853824, 91.722242
sha_transformbb_13, 863842, 92.006701
sha_transformbb_14, 873851, 91.576206
sha_transformbb_10, 883852, 91.599790
sha_transformbb_11, 893867, 91.668506
sha_transformbb_3, 904587, 92.496517
sha_transformbb_5, 914603, 91.722242
sha_transformbb_13, 924614, 91.602253
sha_transformbb_9, 934631, 91.666117
sha_transformbb_10, 944636, 91.654479
sha_transformbb_11, 954645, 91.675161
sha_transformbb_3, 965269, 92.520722
sha_transformbb_5, 975285, 91.722242
sha_transformbb_7, 985298, 91.898802
sha_transformbb_9, 995311, 91.629778
sha_transformbb_10, 1005313, 91.654389
sha_transformbb_11, 1015328, 91.668506
sha_transformbb_3, 1026048, 92.496517
sha_transformbb_5, 1036054, 91.677168
sha_transformbb_7, 1046058, 91.569880
sha_transformbb_14, 1056069, 91.727880
sha_transformbb_15, 1066071, 91.679693
sha_transformbb_11, 1076084, 91.590943
sha_transformbb_3, 1086786, 92.476468
sha_transformbb_5, 1096792, 91.677168
sha_transformbb_7, 1106829, 91.914477
sha_transformbb_14, 1116838, 91.634795
sha_transformbb_10, 1126858, 91.620577
sha_transformbb_11, 1136873, 91.668506
sha_updatebb_6, 1146886, 91.549912
sha_transformbb_3, 1156976, 92.737121
sha_transformbb_5, 1166992, 91.722242
sha_transformbb_13, 1177003, 91.602253
sha_transformbb_9, 1187020, 91.666117
sha_transformbb_10, 1197025, 91.654479
sha_transformbb_11, 1207034, 91.675161
sha_transformbb_3, 1217686, 92.464278
sha_transformbb_5, 1227702, 91.722242
sha_transformbb_13, 1237720, 91.907413
sha_transformbb_9, 1247733, 91.670551
sha_transformbb_10, 1257736, 91.654419
sha_transformbb_11, 1267745, 91.618955
sha_transformbb_2, 1277747, 98.128204
sha_transformbb_3, 1287834, 86.243070
sha_streambb_4, 1297835, 98.823527
sha_streambb_4, 1307837, 107.701716
sha_streambb_4, 1317839, 107.701716
sha_streambb_4, 1327841, 107.701716
sha_streambb_4, 1337843, 107.701716
sha_transformbb_13, 1347848, 95.485851
sha_transformbb_9, 1357853, 89.275945
sha_transformbb_11, 1367855, 89.275229
sha_transformbb_3, 1378074, 89.399531
sha_transformbb_5, 1388078, 89.171053
sha_transformbb_14, 1398092, 89.287533
sha_transformbb_17, 1408097, 89.276118
sha_transformbb_3, 1418430, 89.367862
sha_transformbb_5, 1428434, 89.171053
sha_transformbb_14, 1438443, 89.685348
sha_transformbb_15, 1448446, 91.630310
sha_transformbb_17, 1458447, 91.667935
sha_transformbb_3, 1468929, 92.521568
sha_transformbb_5, 1478945, 91.722242
sha_transformbb_13, 1488956, 91.602253
sha_transformbb_14, 1498969, 91.671146
sha_transformbb_15, 1508972, 91.679720
sha_transformbb_17, 1518983, 91.656846
sha_transformbb_3, 1529625, 92.480919
sha_transformbb_5, 1539631, 91.677168
sha_transformbb_7, 1549682, 91.885413
sha_transformbb_14, 1559696, 91.684309
sha_transformbb_15, 1569697, 91.679666
sha_transformbb_17, 1579708, 91.600652
sha_updatebb_6, 1589711, 91.566702
sha_transformbb_3, 1599815, 92.707069
sha_transformbb_5, 1609831, 91.722242
sha_transformbb_13, 1619842, 91.602253
sha_transformbb_9, 1629859, 91.666117
sha_transformbb_10, 1639864, 91.654479
sha_transformbb_11, 1649873, 91.675161
sha_transformbb_3, 1660525, 92.464278
sha_transformbb_5, 1670541, 91.722242
sha_transformbb_13, 1680559, 91.907413
sha_transformbb_9, 1690572, 91.670551
sha_transformbb_10, 1700575, 91.654419
sha_transformbb_11, 1710588, 91.670723
sha_transformbb_3, 1721276, 92.504537
sha_transformbb_5, 1731282, 91.677168
sha_transformbb_13, 1741297, 91.543947
sha_transformbb_14, 1751306, 91.675584
sha_transformbb_9, 1761310, 91.481022
sha_transformbb_10, 1771324, 91.605391
sha_transformbb_17, 1781333, 91.712246
sha_transformbb_3, 1791523, 92.547467
sha_transformbb_5, 1801534, 91.699716
sha_transformbb_7, 1811552, 91.921224
sha_transformbb_14, 1821561, 91.634795
sha_transformbb_10, 1831562, 91.590595
sha_transformbb_11, 1841581, 91.647991
sha_updatebb_6, 1851609, 91.600396
sha_transformbb_3, 1861727, 92.677100
sha_transformbb_5, 1871738, 91.699716
sha_transformbb_13, 1881751, 91.573094
sha_transformbb_9, 1891766, 91.668333
sha_transformbb_15, 1901778, 91.655879
sha_transformbb_17, 1911787, 91.602856
sha_transformbb_3, 1922507, 92.437030
sha_transformbb_5, 1932513, 91.677168
sha_streambb_4, 1942517, 99.810857
sha_streambb_4, 1952519, 107.701716
sha_streambb_4, 1962521, 107.701716
sha_streambb_4, 1972523, 107.701716
sha_streambb_4, 1982525, 107.701716
sha_transformbb_9, 1992527, 94.118063
sha_transformbb_10, 2002533, 89.262644
sha_transformbb_3, 2013078, 89.405042
sha_transformbb_5, 2023082, 89.171053
sha_transformbb_14, 2033096, 89.287533
sha_transformbb_17, 2043101, 89.276118
sha_transformbb_3, 2053434, 89.367862
sha_transformbb_5, 2063438, 89.171053
sha_transformbb_14, 2073452, 89.287533
sha_transformbb_17, 2083457, 89.724823
sha_transformbb_3, 2094163, 92.465000
sha_transformbb_5, 2104174, 91.699716
sha_transformbb_7, 2114234, 91.834079
sha_transformbb_9, 2124247, 91.629778
sha_transformbb_10, 2134249, 91.654389
sha_transformbb_11, 2144264, 91.668506
sha_transformbb_3, 2154984, 92.496517
sha_transformbb_5, 2165000, 91.722242
sha_transformbb_7, 2175011, 91.547737
sha_transformbb_14, 2185024, 91.725651
sha_transformbb_10, 2195027, 91.599860
sha_transformbb_11, 2205034, 91.621164
sha_transformbb_3, 2215722, 92.504537
sha_transformbb_5, 2225728, 91.677168
sha_transformbb_7, 2235779, 91.885413
sha_transformbb_14, 2245788, 91.634795
sha_transformbb_10, 2255808, 91.620577
sha_transformbb_11, 2265823, 91.668506
sha_transformbb_2, 2275825, 98.327099
sha_transformbb_3, 2285926, 86.025064
sha_transformbb_5, 2295937, 91.699716
sha_transformbb_7, 2305953, 91.570339
sha_transformbb_9, 2315965, 91.671118
sha_transformbb_10, 2325983, 91.625652
sha_transformbb_11, 2335994, 91.672942
sha_transformbb_3, 2346650, 92.512605
sha_transformbb_5, 2356661, 91.699716
sha_transformbb_7, 2366693, 91.892095
sha_transformbb_14, 2376707, 91.684309
sha_transformbb_10, 2386708, 91.599790
sha_transformbb_17, 2396719, 91.680448
sha_updatebb_6, 2406722, 91.566702
sha_transformbb_3, 2416840, 92.677100
sha_transformbb_5, 2426851, 91.699716
sha_transformbb_7, 2436864, 91.518589
sha_transformbb_9, 2446874, 91.673337
sha_transformbb_10, 2456877, 91.654419
sha_transformbb_17, 2466886, 91.682669
sha_transformbb_3, 2477606, 92.437030
sha_transformbb_5, 2487622, 91.722242
sha_transformbb_7, 2497663, 91.840658
sha_transformbb_9, 2507676, 91.629778
sha_transformbb_10, 2517687, 91.566867
sha_transformbb_10, 2527701, 91.623756
sha_transformbb_12, 2537708, 92.040721
sha_transformbb_3, 2547866, 92.234669
sha_transformbb_5, 2557877, 91.699716
sha_transformbb_7, 2567890, 91.518589
sha_transformbb_9, 2577900, 91.673337
sha_streambb_4, 2587904, 102.389867
sha_streambb_4, 2597906, 107.701716
sha_streambb_4, 2607908, 107.701716
sha_streambb_4, 2617910, 107.701716
sha_streambb_4, 2627912, 107.701716
sha_transformbb_17, 2637924, 92.056519
sha_transformbb_3, 2648193, 89.365058
sha_transformbb_5, 2658197, 89.171053
sha_transformbb_14, 2668211, 89.287533
sha_transformbb_17, 2678216, 89.276118
sha_transformbb_3, 2688549, 89.367862
sha_transformbb_5, 2698553, 89.171053
sha_transformbb_14, 2708567, 89.287533
sha_transformbb_17, 2718572, 89.276118
sha_transformbb_3, 2728905, 90.698749
sha_transformbb_5, 2738921, 91.722242
sha_transformbb_13, 2748932, 91.602253
sha_transformbb_9, 2758949, 91.666117
sha_transformbb_10, 2768954, 91.654479
sha_transformbb_11, 2778963, 91.675161
sha_transformbb_3, 2789587, 92.520722
sha_transformbb_5, 2799598, 91.699716
sha_transformbb_7, 2809630, 91.892095
sha_transformbb_14, 2819644, 91.684309
sha_transformbb_15, 2829645, 91.679666
sha_transformbb_11, 2839660, 91.588741
sha_transformbb_3, 2850380, 92.496517
sha_transformbb_5, 2860391, 91.699716
sha_transformbb_7, 2870407, 91.570339
sha_transformbb_9, 2880419, 91.671118
sha_transformbb_15, 2890431, 91.655879
sha_transformbb_11, 2900444, 91.590943
sha_transformbb_3, 2911132, 92.504537
sha_transformbb_5, 2921148, 91.722242
sha_transformbb_13, 2931166, 91.907413
sha_transformbb_14, 2941175, 91.675584
sha_transformbb_10, 2951176, 91.599790
sha_transformbb_11, 2961191, 91.668506
sha_transformbb_2, 2971193, 98.128204
sha_transformbb_3, 2981294, 86.222009
sha_transformbb_5, 2991305, 91.699716
sha_transformbb_13, 3001315, 91.521330
sha_transformbb_9, 3011328, 91.670551
sha_transformbb_10, 3021331, 91.654419
sha_transformbb_17, 3031340, 91.682669
sha_transformbb_2, 3041342, 98.163894
sha_transformbb_3, 3051443, 86.123537
sha_transformbb_5, 3061449, 91.677168
sha_transformbb_7, 3071528, 91.827525
sha_transformbb_9, 3081537, 91.571082
sha_transformbb_9, 3091546, 91.594351
sha_transformbb_15, 3101560, 91.685164
sha_transformbb_17, 3111569, 91.632434
sha_transformbb_3, 3121759, 92.547467
sha_transformbb_5, 3131765, 91.677168
sha_transformbb_13, 3141766, 91.572638
sha_transformbb_14, 3151770, 91.626041
sha_transformbb_16, 3161780, 91.592112
sha_transformbb_15, 3171793, 91.623723
sha_transformbb_11, 3181806, 91.620509
sha_transformbb_3, 3192006, 92.530024
sha_transformbb_5, 3202022, 91.722242
sha_transformbb_7, 3212035, 91.898802
sha_transformbb_14, 3222044, 91.634795
sha_streambb_4, 3232045, 101.941577
sha_streambb_4, 3242047, 107.701716
sha_streambb_4, 3252049, 107.701716
sha_streambb_4, 3262051, 107.701716
sha_streambb_4, 3272053, 108.150556
sha_transformbb_17, 3282063, 91.684059
sha_transformbb_3, 3292332, 89.365058
sha_transformbb_5, 3302336, 89.171053
sha_transformbb_14, 3312350, 89.287533
sha_transformbb_17, 3322355, 89.276118
sha_transformbb_3, 3332688, 89.367862
sha_transformbb_5, 3342692, 89.171053
sha_transformbb_14, 3352706, 89.287533
sha_transformbb_17, 3362711, 89.276118
sha_transformbb_3, 3373044, 90.698749
sha_transformbb_5, 3383060, 91.722242
sha_transformbb_13, 3393078, 91.907413
sha_transformbb_9, 3403091, 91.670551
sha_transformbb_10, 3413108, 91.625619
sha_transformbb_11, 3423121, 91.670723
sha_transformbb_3, 3433809, 92.504537
sha_transformbb_5, 3443815, 91.677168
sha_transformbb_7, 3453819, 91.569880
sha_transformbb_14, 3463830, 91.727880
sha_transformbb_15, 3473832, 91.679693
sha_transformbb_17, 3483841, 91.602856
sha_transformbb_3, 3494547, 92.465000
sha_transformbb_5, 3504563, 91.722242
sha_transformbb_13, 3514581, 91.907413
sha_transformbb_9, 3524594, 91.670551
sha_transformbb_15, 3534605, 91.655849
sha_transformbb_11, 3544620, 91.588741
sha_updatebb_6, 3554633, 91.549912
sha_transformbb_3, 3564737, 92.707069
sha_transformbb_5, 3574748, 91.699716
sha_transformbb_7, 3584764, 91.570339
sha_transformbb_14, 3594777, 91.725651
sha_transformbb_15, 3604780, 91.679720
sha_transformbb_17, 3614787, 91.605062
sha_transformbb_3, 3625475, 92.444871
sha_transformbb_5, 3635491, 91.722242
sha_transformbb_7, 3645504, 91.898802
sha_transformbb_14, 3655518, 91.684309
sha_transformbb_10, 3665528, 91.512308
sha_transformbb_10, 3675542, 91.623756
sha_updatebb_6, 3685589, 91.595935
sha_transformbb_3, 3695665, 92.767257
sha_transformbb_5, 3705681, 91.722242
sha_transformbb_7, 3715692, 91.547737
sha_transformbb_9, 3725704, 91.671118
sha_transformbb_10, 3735722, 91.625652
sha_transformbb_17, 3745729, 91.684890
sha_transformbb_3, 3756431, 92.416881
sha_transformbb_5, 3766437, 91.677168
sha_transformbb_7, 3776474, 91.914477
sha_transformbb_9, 3786487, 91.629778
sha_transformbb_10, 3796503, 91.625586
sha_transformbb_11, 3806517, 91.589301
sha_updatebb_6, 3816545, 91.600396
sha_transformbb_3, 3826649, 92.707069
sha_transformbb_5, 3836665, 91.722242
sha_transformbb_13, 3846676, 91.602253
sha_transformbb_9, 3856688, 91.616608
sha_transformbb_10, 3866706, 91.625652
sha_streambb_4, 3876710, 103.857164
sha_streambb_4, 3886712, 107.701716
sha_streambb_4, 3896714, 107.701716
sha_streambb_4, 3906716, 107.701716
sha_streambb_4, 3916718, 107.701716
sha_transformbb_3, 3927335, 90.614651
sha_transformbb_5, 3937339, 89.171053
sha_transformbb_14, 3947353, 89.287533
sha_transformbb_17, 3957358, 89.276118
sha_transformbb_3, 3967691, 89.367862
sha_transformbb_5, 3977695, 89.171053
sha_transformbb_14, 3987709, 89.287533
sha_transformbb_17, 3997714, 89.276118
sha_transformbb_3, 4008061, 89.343075
sha_transformbb_5, 4018065, 90.674686
sha_transformbb_13, 4028070, 91.627416
sha_transformbb_9, 4038076, 91.649871
sha_transformbb_15, 4048085, 91.685030
sha_transformbb_11, 4058094, 91.638240
sha_transformbb_3, 4068412, 92.575411
sha_transformbb_5, 4078428, 91.722242
sha_transformbb_13, 4088446, 91.907413
sha_transformbb_14, 4098455, 91.675584
sha_transformbb_10, 4108470, 91.571060
sha_transformbb_11, 4118485, 91.668506
sha_transformbb_3, 4129205, 92.496517
sha_transformbb_5, 4139221, 91.722242
sha_transformbb_7, 4149232, 91.547737
sha_transformbb_9, 4159244, 91.671118
sha_transformbb_10, 4169248, 91.654449
sha_transformbb_17, 4179255, 91.684890
sha_transformbb_3, 4189957, 92.416881
sha_transformbb_5, 4199973, 91.722242
sha_transformbb_7, 4209986, 91.898802
sha_transformbb_14, 4219995, 91.634795
sha_transformbb_10, 4230015, 91.620577
sha_transformbb_17, 4240026, 91.680448
sha_updatebb_6, 4250029, 91.566702
sha_transformbb_3, 4260119, 92.737121
sha_transformbb_5, 4270135, 91.722242
sha_transformbb_7, 4280146, 91.547737
sha_transformbb_9, 4290158, 91.671118
sha_transformbb_10, 4300162, 91.654449
sha_transformbb_17, 4310169, 91.684890
sha_transformbb_3, 4320913, 92.333346
sha_transformbb_5, 4330929, 91.722242
sha_transformbb_7, 4340942, 91.898802
sha_transformbb_14, 4350956, 91.684309
sha_transformbb_10, 4360957, 91.599790
sha_transformbb_11, 4370971, 91.589301
sha_updatebb_6, 4380985, 91.629129
sha_transformbb_3, 4391103, 92.677100
sha_transformbb_5, 4401114, 91.699716
sha_transformbb_13, 4411127, 91.573094
sha_transformbb_9, 4421137, 91.618816
sha_transformbb_10, 4431154, 91.625619
sha_transformbb_17, 4441163, 91.682669
sha_updatebb_6, 4451176, 91.486224
sha_transformbb_3, 4461294, 92.677100
sha_transformbb_5, 4471300, 91.677168
sha_transformbb_7, 4481351, 91.885413
sha_transformbb_14, 4491360, 91.634795
sha_transformbb_10, 4501361, 91.590595
sha_transformbb_18, 4511375, 91.696620
sha_streambb_4, 4521380, 104.050000
sha_streambb_4, 4531382, 107.701716
sha_streambb_4, 4541384, 107.701716
sha_streambb_4, 4551386, 107.701716
sha_streambb_4, 4561388, 108.150556
sha_transformbb_3, 4571397, 89.186194
sha_transformbb_5, 4581404, 89.157573
sha_transformbb_14, 4591418, 89.260582
sha_transformbb_17, 4601424, 89.274110
sha_transformbb_3, 4611789, 89.369252
sha_transformbb_5, 4621793, 89.171053
sha_transformbb_14, 4631807, 89.287533
sha_transformbb_17, 4641812, 89.276118
sha_transformbb_3, 4652159, 89.343075
sha_transformbb_5, 4662163, 90.674686
sha_transformbb_7, 4672178, 91.929879
sha_transformbb_9, 4682191, 91.628272
sha_transformbb_10, 4692198, 91.605148
sha_transformbb_17, 4702203, 91.673793
sha_transformbb_3, 4712621, 92.538177
sha_transformbb_5, 4722637, 91.722242
sha_transformbb_13, 4732648, 91.602253
sha_transformbb_9, 4742665, 91.666117
sha_transformbb_10, 4752670, 91.654479
sha_transformbb_11, 4762679, 91.675161
sha_transformbb_3, 4773345, 92.436167
sha_transformbb_5, 4783361, 91.722242
sha_transformbb_7, 4793374, 91.898802
sha_transformbb_14, 4803388, 91.684309
sha_transformbb_15, 4813389, 91.679666
sha_transformbb_11, 4823404, 91.588741
sha_updatebb_6, 4833417, 91.549912
sha_transformbb_3, 4843493, 92.767257
sha_transformbb_5, 4853504, 91.699716
sha_transformbb_7, 4863520, 91.570339
sha_transformbb_9, 4873532, 91.671118
sha_transformbb_10, 4883536, 91.654449
sha_transformbb_11, 4893547, 91.672942
sha_transformbb_3, 4904231, 92.456352
sha_transformbb_5, 4914237, 91.677168
sha_transformbb_7, 4924288, 91.885413
sha_transformbb_9, 4934301, 91.629778
sha_transformbb_10, 4944303, 91.654389
sha_transformbb_11, 4954318, 91.668506
sha_updatebb_6, 4964331, 91.549912
sha_transformbb_3, 4974407, 92.767257
sha_transformbb_5, 4984418, 91.699716
sha_transformbb_13, 4994431, 91.573094
sha_transformbb_14, 5004437, 91.623830
sha_transformbb_10, 5014452, 91.571060
sha_transformbb_11, 5024467, 91.668506
sha_transformbb_2, 5034469, 98.227652
sha_transformbb_3, 5044556, 86.144460
sha_transformbb_5, 5054562, 91.677168
sha_transformbb_7, 5064599, 91.914477
sha_transformbb_9, 5074612, 91.629778
sha_transformbb_10, 5084628, 91.625586
sha_transformbb_11, 5094642, 91.589301
sha_updatebb_6, 5104684, 91.571742
sha_transformbb_3, 5114774, 92.737121
sha_transformbb_5, 5124785, 91.699716
sha_transformbb_7, 5134798, 91.518589
sha_transformbb_9, 5144808, 91.673337
sha_transformbb_10, 5154825, 91.625619
sha_streambb_4, 5164827, 103.428919
sha_streambb_4, 5174829, 107.701716
sha_streambb_4, 5184831, 108.150556
sha_streambb_4, 5194833, 107.701716
sha_streambb_4, 5204835, 107.701716
sha_transformbb_3, 5215474, 90.619242
sha_transformbb_5, 5225478, 89.171053
sha_transformbb_14, 5235492, 89.287533
sha_transformbb_17, 5245497, 89.276118
sha_transformbb_3, 5255830, 89.367862
sha_transformbb_5, 5265834, 89.171053
sha_transformbb_14, 5275848, 89.287533
sha_transformbb_17, 5285853, 89.276118
sha_transformbb_3, 5296186, 89.367862
sha_transformbb_5, 5306190, 90.674686
sha_transformbb_7, 5316198, 91.624643
sha_transformbb_14, 5326202, 91.707236
sha_transformbb_15, 5336216, 91.680020
sha_transformbb_11, 5346223, 91.640453
sha_transformbb_3, 5356495, 92.613342
sha_transformbb_5, 5366506, 91.699716
sha_transformbb_7, 5376538, 91.892095
sha_transformbb_14, 5386552, 91.684309
sha_transformbb_15, 5396553, 91.679666
sha_transformbb_11, 5406554, 91.617496
sha_updatebb_6, 5416567, 91.549912
sha_transformbb_3, 5426643, 92.767257
sha_transformbb_5, 5436654, 91.699716
sha_transformbb_13, 5446667, 91.573094
sha_transformbb_9, 5456682, 91.668333
sha_transformbb_10, 5466700, 91.625652
sha_transformbb_17, 5476707, 91.684890
sha_transformbb_3, 5487395, 92.444871
sha_transformbb_5, 5497411, 91.722242
sha_transformbb_13, 5507429, 91.907413
sha_transformbb_9, 5517437, 91.621025
sha_transformbb_10, 5527453, 91.625586
sha_transformbb_11, 5537468, 91.668506
sha_transformbb_3, 5548188, 92.496517
sha_transformbb_5, 5558199, 91.699716
sha_transformbb_7, 5568215, 91.570339
sha_transformbb_9, 5578222, 91.621587
sha_transformbb_10, 5588225, 91.654419
sha_transformbb_11, 5598238, 91.670723
sha_transformbb_3, 5608940, 92.476468
sha_transformbb_5, 5618951, 91.699716
sha_transformbb_7, 5628983, 91.892095
sha_transformbb_9, 5638996, 91.629778
sha_transformbb_15, 5649006, 91.655819
sha_transformbb_18, 5659007, 91.636481
sha_updatebb_6, 5669054, 91.523311
sha_transformbb_3, 5679158, 92.707069
sha_transformbb_5, 5689174, 91.722242
sha_transformbb_13, 5699185, 91.602253
sha_transformbb_14, 5709198, 91.671146
sha_transformbb_10, 5719215, 91.571136
sha_transformbb_11, 5729226, 91.672942
sha_transformbb_3, 5739924, 92.428336
sha_transformbb_5, 5749930, 91.677168
sha_transformbb_7, 5759995, 91.856429
sha_transformbb_14, 5770009, 91.684309
sha_transformbb_10, 5780010, 91.599790
sha_transformbb_11, 5790025, 91.668506
sha_updatebb_7, 5800038, 91.543003
sha_streambb_4, 5810039, 105.648856
sha_streambb_4, 5820041, 107.701716
sha_streambb_4, 5830043, 107.701716
sha_streambb_4, 5840045, 107.701716
sha_transformbb_3, 5850338, 106.228937
sha_transformbb_5, 5860345, 89.001298
sha_transformbb_14, 5870355, 89.279644
sha_transformbb_15, 5880363, 89.288470
sha_transformbb_3, 5890792, 89.354371
sha_transformbb_5, 5900796, 89.171053
sha_transformbb_14, 5910810, 89.287533
sha_transformbb_17, 5920815, 89.276118
sha_transformbb_3, 5931148, 89.464124
sha_transformbb_5, 5941166, 89.046438
sha_transformbb_14, 5951170, 91.089291
sha_transformbb_15, 5961173, 91.679720
sha_transformbb_17, 5971184, 91.656846
sha_transformbb_3, 5981840, 92.452760
sha_transformbb_5, 5991856, 91.722242
sha_transformbb_13, 6001867, 91.602253
sha_transformbb_14, 6011875, 91.621620
sha_transformbb_15, 6021877, 91.679693
sha_transformbb_11, 6031890, 91.590943
sha_transformbb_3, 6042606, 92.448473
sha_transformbb_5, 6052622, 91.722242
sha_transformbb_13, 6062640, 91.907413
sha_transformbb_9, 6072653, 91.670551
sha_transformbb_10, 6082656, 91.654419
sha_transformbb_11, 6092665, 91.618955
sha_transformbb_3, 6103399, 92.468543
sha_transformbb_5, 6113405, 91.677168
sha_transformbb_13, 6123406, 91.572638
sha_transformbb_14, 6133415, 91.675584
sha_transformbb_10, 6143416, 91.599790
sha_transformbb_11, 6153431, 91.668506
sha_transformbb_3, 6164151, 92.496517
sha_transformbb_5, 6174162, 91.699716
sha_transformbb_7, 6184180, 91.921224
sha_transformbb_14, 6194189, 91.634795
sha_transformbb_10, 6204209, 91.620577
sha_transformbb_17, 6214220, 91.680448
sha_transformbb_12, 6224225, 91.925323
sha_transformbb_3, 6234369, 92.263909
sha_transformbb_5, 6244375, 91.677168
sha_transformbb_7, 6254379, 91.569880
sha_transformbb_14, 6264390, 91.727880
sha_transformbb_15, 6274400, 91.601298
sha_transformbb_17, 6284411, 91.600652
sha_updatebb_6, 6294442, 91.509427
sha_transformbb_3, 6304532, 92.737121
sha_transformbb_5, 6314543, 91.699716
sha_transformbb_7, 6324617, 91.805193
sha_transformbb_9, 6334626, 91.571082
sha_transformbb_16, 6344636, 91.655819
sha_transformbb_10, 6354655, 91.593519
sha_transformbb_11, 6364658, 91.598940
sha_transformbb_3, 6374848, 92.610049
sha_transformbb_5, 6384864, 91.722242
sha_transformbb_7, 6394875, 91.547737
sha_transformbb_14, 6404888, 91.725651
sha_transformbb_10, 6414899, 91.521537
sha_transformbb_11, 6424912, 91.670723
sha_transformbb_3, 6435628, 92.448473
sha_streambb_4, 6445630, 91.965380
sha_streambb_4, 6455636, 107.010070
sha_streambb_4, 6465638, 107.701716
sha_streambb_4, 6475640, 107.701716
sha_streambb_4, 6485642, 108.150556
sha_transformbb_5, 6495658, 104.106871
sha_transformbb_9, 6505666, 89.208987
sha_transformbb_11, 65156
\ No newline at end of file
instrument/examples/sha/instrumented_power/sha.h 0 → 100644
View file @ d126c154
#ifndef SHA_H
#define SHA_H
/* NIST Secure Hash Algorithm */
/* heavily modified from Peter C. Gutmann's implementation */
/* Useful defines & typedefs */
typedef unsigned char BYTE;
typedef unsigned long LONG;
#define SHA_BLOCKSIZE 64
#define SHA_DIGESTSIZE 20
struct SHA_INFO {
unsigned long digest[5]; /* message digest */
unsigned long count_lo, count_hi; /* 64-bit bit count */
unsigned long data[16]; /* SHA data buffer */
};
void sha_init (struct SHA_INFO *sha_info, unsigned long sha_info_addr);
void sha_update (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsigned char *buffer, unsigned long buffer_addr, int count);
void sha_final (struct SHA_INFO *sha_info, unsigned long sha_info_addr);
void sha_stream (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsigned char *inData, unsigned long inData_addr, unsigned long int dSize);
void sha_print (struct SHA_INFO *sha_info, unsigned long sha_info_addr);
#endif /* SHA_H */
instrument/examples/sha/instrumented_power/sha_IR.c 0 → 100644
View file @ d126c154
/***********************************************************
Intermediate representation of
sha/app_dir/sha.c
Converted by ir2c v0.1
***********************************************************/
#include <limits.h>
#include <stdint.h>
#include "ir2c.h"
#include "cacheSim.h"
#include "branchPred.h"
#include "power_estimator.h"
extern unsigned long SP;
extern unsigned long long memAccessCycles;
extern unsigned long long pipelineCycles;
extern struct csim_result_t csim_result;
/* NIST Secure Hash Algorithm */
/* heavily modified by Uwe Hollerbach uh@alumni.caltech edu */
/* from Peter C. Gutmann's implementation as found in */
/* Applied Cryptography by Bruce Schneier */
/* NIST's proposed modification to SHA of 7/11/94 may be */
/* activated by defining USE_MODIFIED_SHA */
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include "sha.h"
#include "my_mem.h"
//#include "my_defines.h"
//#include "my_variable.h"
/* SHA f()-functions */
extern unsigned int ARR_SIZE;
extern unsigned long ARR_SIZE_addr;
#define f1(x,y,z) ((x & y) | (~x & z))
#define f2(x,y,z) (x ^ y ^ z)
#define f3(x,y,z) ((x & y) | (x & z) | (y & z))
#define f4(x,y,z) (x ^ y ^ z)
/* SHA constants */
#define CONST1 0x5a827999L
#define CONST2 0x6ed9eba1L
#define CONST3 0x8f1bbcdcL
#define CONST4 0xca62c1d6L
/* 32-bit rotate */
#define ROT32(x,n) ((x << n) | (x >> (32 - n)))
#define FUNC(n,i) \
temp = ROT32(A,5) + f##n(B,C,D) + E + W[i] + CONST##n; \
E = D; D = C; C = ROT32(B,30); B = A; A = temp
/* do SHA transformation */
static void sha_transform (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
long unsigned int A_133;
long unsigned int E_132;
uintptr_t D_131;
long unsigned int B_130;
long unsigned int A_129;
long unsigned int E_128;
uintptr_t D_127;
long unsigned int B_126;
long unsigned int A_125;
long unsigned int E_124;
long unsigned int E_123;
uintptr_t D_122;
uintptr_t D_121;
long unsigned int B_120;
long unsigned int B_119;
long unsigned int A_118;
long unsigned int A_117;
uintptr_t ivtmp_116;
unsigned long ivtmp_116_addr; // GK
uintptr_t ivtmp_115;
unsigned long ivtmp_115_addr; // GK
long unsigned int C_114;
long unsigned int temp_113;
long unsigned int C_105;
long unsigned int temp_104;
long unsigned int C_101;
long unsigned int temp_100;
long unsigned int C_97;
uintptr_t ivtmp_94;
unsigned long ivtmp_94_addr;
uintptr_t ivtmp_93;
uintptr_t D_2940;
uintptr_t ivtmp_79;
unsigned long ivtmp_79_addr;
uintptr_t ivtmp_71;
uintptr_t D_2917;
uintptr_t ivtmp_63;
unsigned long ivtmp_63_addr; // GK
long unsigned int W[80];
unsigned long W_addr = 0x10;
long unsigned int E;
long unsigned int D;
long unsigned int C;
long unsigned int B;
long unsigned int A;
long unsigned int temp;
sha_transformbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x170;
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x230, 20, &csim_result);
estimate_power("sha_transformbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0xa4, 0xa8) ? 7 : 0);
ivtmp_94 = (uintptr_t)sha_info;
ivtmp_94_addr = sha_info_addr;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
ivtmp_93 = 0;
// # SUCC: 3 [100.0%] (fallthru,exec)
sha_transformbb_3:
// # PRED: 3 [94.1%] (true,exec) 2 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + W_addr + (+ivtmp_93)), 0, &csim_result);
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x244, 28, &csim_result);
memAccessCycles += simDCache(ivtmp_94_addr + 28, 1, &csim_result); // GK from line + 2
estimate_power("sha_transformbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar sha_info at line 170 -- Done
pipelineCycles += 12 - (enterBlock(0xa9, 0xaf) ? 7 : 0);
*(long unsigned int*)((uintptr_t)&W + (uintptr_t)ivtmp_93) = *(long unsigned int*)((uintptr_t)ivtmp_94 + 28);
ivtmp_93 = ivtmp_93 + 4;
ivtmp_94 = ivtmp_94 + 4;
ivtmp_94_addr = ivtmp_94_addr + 4;
if (ivtmp_93 != 64)
goto sha_transformbb_3;
else
goto sha_transformbb_4;
// # SUCC: 3 [94.1%] (true,exec) 4 [5.9%] (false,exec)
sha_transformbb_4:
// # PRED: 3 [5.9%] (false,exec)
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x260, 8, &csim_result);
estimate_power("sha_transformbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0xb0, 0xb1) ? 7 : 0);
ivtmp_79 = (uintptr_t)&W[13];
ivtmp_79_addr = W_addr + 13 * sizeof(unsigned long); // GK
ivtmp_63 = (uintptr_t)&W;
ivtmp_63_addr = W_addr; // GK
D_2940 = ivtmp_63 + 308;
// # SUCC: 5 [100.0%] (fallthru,exec)
sha_transformbb_5:
// # PRED: 5 [98.5%] (true,exec) 4 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x268, 44, &csim_result);
estimate_power("sha_transformbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 178 -- Done
memAccessCycles += simDCache(ivtmp_79_addr + 4294967276, 1, &csim_result); // GK
// TODO: UnmappedLS: Load LocalVar W at line 179 -- Done
memAccessCycles += simDCache(ivtmp_79_addr, 1, &csim_result); // GK
// TODO: UnmappedLS: Load LocalVar W at line 181 -- Done
memAccessCycles += simDCache(ivtmp_79_addr + 4294967252, 1, &csim_result); // GK
// TODO: UnmappedLS: Load LocalVar W at line 183 -- Done
memAccessCycles += simDCache(ivtmp_79_addr + 4294967244, 1, &csim_result); // GK
// TODO: UnmappedLS: Store LocalVar W at line 185 --Done
memAccessCycles += simDCache(ivtmp_79_addr + 12, 0, &csim_result); // GK
pipelineCycles += 23 - (enterBlock(0xb2, 0xbc) ? 7 : 0);
*(long unsigned int*)((uintptr_t)ivtmp_79 + 12) = ((*(long unsigned int*)((uintptr_t)ivtmp_79 + (int)4294967276) ^ *(long unsigned int*)((uintptr_t)ivtmp_79)) ^ *(long unsigned int*)((uintptr_t)ivtmp_79 + (int)4294967252)) ^ *(long unsigned int*)((uintptr_t)ivtmp_79 + (int)4294967244);
ivtmp_79 = ivtmp_79 + 4;
ivtmp_79_addr = ivtmp_79_addr + 4; // GK
if (ivtmp_79 != D_2940)
goto sha_transformbb_5;
else
goto sha_transformbb_6;
// # SUCC: 5 [98.5%] (true,exec) 6 [1.5%] (false,exec)
sha_transformbb_6:
// # PRED: 5 [1.5%] (false,exec)
memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache((SP + 0x8), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache((SP + 0x0), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x8), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache(0x460, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 4
memAccessCycles += simICache(0x294, 68, &csim_result);
estimate_power("sha_transformbb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar sha_info at line 189 -- Done
// TODO: UnmappedLS: Load GlobalVar sha_info at line 190 -- Done
// TODO: UnmappedLS: Load GlobalVar sha_info at line 192 -- Done
// TODO: UnmappedLS: Load GlobalVar sha_info at line 194 -- Done
// TODO: UnmappedLS: Load GlobalVar sha_info at line 196 -- Done
pipelineCycles += 24 - (enterBlock(0xbd, 0xcd) ? 7 : 0);
A = sha_info->digest[0];
memAccessCycles += simDCache(sha_info_addr + 0, 1, &csim_result);
B = sha_info->digest[1];
memAccessCycles += simDCache(sha_info_addr + 4, 1, &csim_result);
C = sha_info->digest[2];
memAccessCycles += simDCache(sha_info_addr + 8, 1, &csim_result);
D = sha_info->digest[3];
memAccessCycles += simDCache(sha_info_addr + 12, 1, &csim_result);
E = sha_info->digest[4];
memAccessCycles += simDCache(sha_info_addr + 16, 1, &csim_result);
A_133 = A;
ivtmp_71 = 0;
// # SUCC: 7 [100.0%] (fallthru,exec)
sha_transformbb_7:
// # PRED: 13 [100.0%] (fallthru) 6 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 5
memAccessCycles += simICache(0x2d8, 48, &csim_result);
estimate_power("sha_transformbb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 206 -- Done
memAccessCycles += simDCache(W_addr + ivtmp_71, 1, &csim_result); // GK
pipelineCycles += 16 - (enterBlock(0xce, 0xd9) ? 7 : 0);
temp = (((*(long unsigned int*)((uintptr_t)&W + (uintptr_t)ivtmp_71) + 1518500249) + E) + ((A_133<<27)|(A_133>>(sizeof(A_133)*CHAR_BIT-27)))) + (~B & D | C & B);
C_97 = (B<<2)|(B>>(sizeof(B)*CHAR_BIT-2));
ivtmp_71 = ivtmp_71 + 4;
if (ivtmp_71 != 80)
goto sha_transformbb_13;
else
goto sha_transformbb_8;
// # SUCC: 13 [95.2%] (true,exec) 8 [4.8%] (false,exec)
sha_transformbb_13:
// # PRED: 7 [95.2%] (true,exec)
// Simulating I Cache for obj block 6
memAccessCycles += simICache(0x308, 24, &csim_result);
estimate_power("sha_transformbb_13", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0xda, 0xdf) ? 7 : 0);
E = D;
D = C;
C = C_97;
B = A_133;
A_133 = temp;
goto sha_transformbb_7;
// # SUCC: 7 [100.0%] (fallthru)
sha_transformbb_8:
// # PRED: 7 [4.8%] (false,exec)
memAccessCycles += simDCache(0x464, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 7
memAccessCycles += simICache(0x320, 16, &csim_result);
estimate_power("sha_transformbb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0xe0, 0xe3) ? 7 : 0);
D_2917 = ivtmp_63 + 80;
ivtmp_116 = ivtmp_63;
ivtmp_116_addr = ivtmp_63_addr; // GK
E_132 = D;
D_131 = C;
B_130 = A_133;
A_129 = temp;
// # SUCC: 9 [100.0%] (fallthru,exec)
sha_transformbb_9:
// # PRED: 14 [100.0%] (fallthru) 8 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 8
memAccessCycles += simICache(0x330, 44, &csim_result);
estimate_power("sha_transformbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 228 -- Done
memAccessCycles += simDCache(ivtmp_116_addr + 80, 1, &csim_result); // GK
pipelineCycles += 17 - (enterBlock(0xe4, 0xee) ? 7 : 0);
temp_100 = (((*(long unsigned int*)((uintptr_t)ivtmp_116 + 80) + 1859775393) + E_132) + ((A_129<<27)|(A_129>>(sizeof(A_129)*CHAR_BIT-27)))) + ((C_97 ^ B_130) ^ D_131);
C_101 = (B_130<<2)|(B_130>>(sizeof(B_130)*CHAR_BIT-2));
ivtmp_116 = ivtmp_116 + 4;
ivtmp_116_addr = ivtmp_116_addr + 4; // GK
if (ivtmp_116 != D_2917)
goto sha_transformbb_14;
else
goto sha_transformbb_16;
// # SUCC: 14 [95.2%] (true,exec) 16 [4.8%] (false,exec)
sha_transformbb_16:
// # PRED: 9 [4.8%] (false,exec)
memAccessCycles += simDCache(0x468, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 10
memAccessCycles += simICache(0x374, 16, &csim_result);
estimate_power("sha_transformbb_16", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0xf5, 0xf8) ? 7 : 0);
ivtmp_115 = ivtmp_63;
ivtmp_115_addr = ivtmp_63_addr; // GK
E_128 = D_131;
D_127 = C_97;
B_126 = A_129;
A_125 = temp_100;
goto sha_transformbb_10;
// # SUCC: 10 [100.0%] (fallthru)
sha_transformbb_14:
// # PRED: 9 [95.2%] (true,exec)
// Simulating I Cache for obj block 9
memAccessCycles += simICache(0x35c, 24, &csim_result);
estimate_power("sha_transformbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0xef, 0xf4) ? 7 : 0);
E_132 = D_131;
D_131 = C_97;
C_97 = C_101;
B_130 = A_129;
A_129 = temp_100;
goto sha_transformbb_9;
// # SUCC: 9 [100.0%] (fallthru)
sha_transformbb_15:
// # PRED: 10 [95.2%] (true,exec)
// Simulating I Cache for obj block 12
memAccessCycles += simICache(0x3b8, 24, &csim_result);
estimate_power("sha_transformbb_15", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0x106, 0x10b) ? 7 : 0);
E_128 = D_127;
D_127 = C_101;
C_101 = C_105;
B_126 = A_125;
A_125 = temp_104;
// # SUCC: 10 [100.0%] (fallthru)
sha_transformbb_10:
// # PRED: 15 [100.0%] (fallthru) 16 [100.0%] (fallthru)
// Simulating I Cache for obj block 11
memAccessCycles += simICache(0x384, 52, &csim_result);
estimate_power("sha_transformbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 249 -- Done
memAccessCycles += simDCache(ivtmp_115_addr + 160, 1, &csim_result); // GK
pipelineCycles += 18 - (enterBlock(0xf9, 0x105) ? 7 : 0);
temp_104 = (((*(long unsigned int*)((uintptr_t)ivtmp_115 + 160) + (int)2400959708) + E_128) + ((A_125<<27)|(A_125>>(sizeof(A_125)*CHAR_BIT-27)))) + ((D_127 | C_101) & B_126 | D_127 & C_101);
C_105 = (B_126<<2)|(B_126>>(sizeof(B_126)*CHAR_BIT-2));
ivtmp_115 = ivtmp_115 + 4;
ivtmp_115_addr = ivtmp_115_addr + 4;
if (ivtmp_115 != D_2917)
goto sha_transformbb_15;
else
goto sha_transformbb_18;
// # SUCC: 15 [95.2%] (true,exec) 18 [4.8%] (false,exec)
sha_transformbb_18:
// # PRED: 10 [4.8%] (false,exec)
memAccessCycles += simDCache(0x46c, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 13
memAccessCycles += simICache(0x3d0, 8, &csim_result);
estimate_power("sha_transformbb_18", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0x10c, 0x10d) ? 7 : 0);
E_123 = D_127;
D_121 = C_101;
B_119 = A_125;
A_117 = temp_104;
// # SUCC: 11 [100.0%] (fallthru)
sha_transformbb_11:
// # PRED: 17 [100.0%] (fallthru) 18 [100.0%] (fallthru)
// Simulating I Cache for obj block 14
memAccessCycles += simICache(0x3d8, 44, &csim_result);
estimate_power("sha_transformbb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar W at line 270 -- Done
memAccessCycles += simDCache(ivtmp_63_addr + 240 + 3395469782, 1, &csim_result); // GK
pipelineCycles += 17 - (enterBlock(0x10e, 0x118) ? 7 : 0);
temp_113 = (((*(long unsigned int*)((uintptr_t)ivtmp_63 + 240) + (int)3395469782) + E_123) + ((A_117<<27)|(A_117>>(sizeof(A_117)*CHAR_BIT-27)))) + ((C_105 ^ B_119) ^ D_121);
C_114 = (B_119<<2)|(B_119>>(sizeof(B_119)*CHAR_BIT-2));
ivtmp_63 = ivtmp_63 + 4;
ivtmp_63_addr = ivtmp_63_addr + 4;
if (ivtmp_63 != D_2917)
goto sha_transformbb_17;
else
goto sha_transformbb_19;
// # SUCC: 17 [95.2%] (true,exec) 19 [4.8%] (false,exec)
sha_transformbb_17:
// # PRED: 11 [95.2%] (true,exec)
// Simulating I Cache for obj block 15
memAccessCycles += simICache(0x404, 24, &csim_result);
estimate_power("sha_transformbb_17", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0x119, 0x11e) ? 7 : 0);
E_123 = D_121;
D_121 = C_105;
C_105 = C_114;
B_119 = A_117;
A_117 = temp_113;
goto sha_transformbb_11;
// # SUCC: 11 [100.0%] (fallthru)
sha_transformbb_19:
// # PRED: 11 [4.8%] (false,exec)
memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x8), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x0), 1, &csim_result); // Reading Spilt Register
pipelineCycles += 34 - (enterBlock(0x11f, 0x12f) ? 7 : 0);
E_124 = D_121;
D_122 = C_105;
B_120 = A_117;
A_118 = temp_113;
// # SUCC: 12 [100.0%] (fallthru)
sha_transformbb_12:
// # PRED: 19 [100.0%] (fallthru)
// Simulating I Cache for obj block 16
memAccessCycles += simICache(0x41c, 68, &csim_result);
estimate_power("sha_transformbb_12", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Store GlobalVar sha_info at line 288 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 291 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 294 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 297 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 300 -- Done
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
sha_info->digest[0] = A_118 + A;
memAccessCycles += simDCache(sha_info_addr + 4, 0, &csim_result);
memAccessCycles += simDCache(sha_info_addr + 4, 1, &csim_result);
sha_info->digest[1] = B_120 + sha_info->digest[1];
memAccessCycles += simDCache(sha_info_addr + 8, 0, &csim_result);
memAccessCycles += simDCache(sha_info_addr + 8, 1, &csim_result);
sha_info->digest[2] = C_114 + sha_info->digest[2];
memAccessCycles += simDCache(sha_info_addr + 12, 0, &csim_result);
memAccessCycles += simDCache(sha_info_addr + 12, 1, &csim_result);
sha_info->digest[3] = D_122 + sha_info->digest[3];
memAccessCycles += simDCache(sha_info_addr + 16, 0, &csim_result);
memAccessCycles += simDCache(sha_info_addr + 16, 1, &csim_result);
sha_info->digest[4] = E_124 + sha_info->digest[4];
return;
// # SUCC: EXIT [100.0%]
}
void sha_init (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
sha_initbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x0;
memAccessCycles += simDCache(0x4b4, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x4b8, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x4bc, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x4c0, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x470, 68, &csim_result);
estimate_power("sha_initbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Store GlobalVar sha_info at line 311 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 316 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 318 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 320 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 322 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 324 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 325 -- Done
pipelineCycles += 23 - (enterBlock(0x136, 0x146) ? 7 : 0);
sha_info->digest[0] = 1732584193;
memAccessCycles += simDCache(sha_info_addr + 0, 0, &csim_result);
sha_info->digest[1] = 4023233417;
memAccessCycles += simDCache(sha_info_addr + 4, 0, &csim_result);
sha_info->digest[2] = 2562383102;
memAccessCycles += simDCache(sha_info_addr + 8, 0, &csim_result);
sha_info->digest[3] = 271733878;
memAccessCycles += simDCache(sha_info_addr + 12, 0, &csim_result);
sha_info->digest[4] = 3285377520;
memAccessCycles += simDCache(sha_info_addr + 16, 0, &csim_result);
sha_info->count_lo = 0;
memAccessCycles += simDCache(sha_info_addr + 20, 0, &csim_result);
sha_info->count_hi = 0;
memAccessCycles += simDCache(sha_info_addr + 24, 0, &csim_result);
return;
// # SUCC: EXIT [100.0%]
}
void sha_print (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
sha_printbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x10;
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x718, 44, &csim_result);
estimate_power("sha_printbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 16 - (enterBlock(0x1e8, 0x1f2) ? 7 : 0);
printf (&"%08lx %08lx %08lx %08lx %08lx\n"[0], sha_info->digest[0], sha_info->digest[1], sha_info->digest[2], sha_info->digest[3], sha_info->digest[4]);
return;
// # SUCC: EXIT [100.0%]
}
void sha_final (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
int count_203;
long unsigned int hi_bit_count;
long unsigned int lo_bit_count;
int count;
long unsigned int * D_2805;
unsigned long D_2805_addr;
sha_finalbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x18;
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x58c, 60, &csim_result);
estimate_power("sha_finalbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Store GlobalVar sha_info at line 393 -- Done
pipelineCycles += 23 - (enterBlock(0x181, 0x18f) ? 7 : 0);
lo_bit_count = sha_info->count_lo;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
hi_bit_count = sha_info->count_hi;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
count = (int) (lo_bit_count >> 3) & 63;
D_2805 = &sha_info->data;
D_2805_addr = sha_info_addr + 28;
memAccessCycles += simDCache(D_2805_addr + count, 0, &csim_result); // GK
*(unsigned char*)( (uintptr_t)D_2805 + (unsigned int) count) = 128;
count_203 = count + 1;
if (count_203 > 56)
goto sha_finalbb_3;
else
goto sha_finalbb_4;
// # SUCC: 3 [39.0%] (true,exec) 4 [61.0%] (false,exec)
sha_finalbb_3:
// # PRED: 2 [39.0%] (true,exec)
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x5ec, 8, &csim_result);
estimate_power("sha_finalbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 8 - (enterBlock(0x199, 0x19a) ? 7 : 0);
my_memset (D_2805 + (unsigned int) count_203, D_2805_addr, 0, (size_t) (64 - count_203));
sha_transform (sha_info, sha_info_addr);
my_memset (D_2805, D_2805_addr, 0, 56);
goto sha_finalbb_5;
// # SUCC: 5 [100.0%] (fallthru,exec)
sha_finalbb_4:
// # PRED: 2 [61.0%] (false,exec)
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x5c8, 36, &csim_result);
estimate_power("sha_finalbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0x190, 0x198) ? 7 : 0);
my_memset (D_2805 + (unsigned int) count_203, D_2805_addr, 0, (size_t) (56 - count_203));
// # SUCC: 5 [100.0%] (fallthru,exec)
sha_finalbb_5:
// # PRED: 3 [100.0%] (fallthru,exec) 4 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x5f4, 24, &csim_result);
estimate_power("sha_finalbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Store GlobalVar sha_info at line 411 -- Already
// TODO: UnmappedLS: Store GlobalVar sha_info at line 412 -- Already
pipelineCycles += 16 - (enterBlock(0x19b, 0x1a0) ? 7 : 0);
sha_info->data[14] = hi_bit_count;
memAccessCycles += simDCache(sha_info_addr + 28 + 13 * 4, 0, &csim_result);
sha_info->data[15] = lo_bit_count;
memAccessCycles += simDCache(sha_info_addr + 28 + 14 * 4, 0, &csim_result);
sha_transform (sha_info, sha_info_addr);
return;
// # SUCC: EXIT [100.0%]
}
void sha_update (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsigned char *buffer, unsigned long buffer_addr, int count) {
uintptr_t D_3103;
unsigned long D_3103_addr;
uintptr_t ivtmp_232;
int D_3089;
uintptr_t D_3086;
long unsigned int * D_2795;
unsigned long D_2795_addr;
long unsigned int D_2787;
long unsigned int count_1;
long unsigned int D_2785;
sha_updatebb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x30;
pipelineCycles += 32 - (enterBlock(0x14d, 0x160) ? 7 : 0);
D_2785 = sha_info->count_lo;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
count_1 = (long unsigned int) count;
D_2787 = count_1 << 3;
if (D_2785 > D_2787 + D_2785)
goto sha_updatebb_3;
else
goto sha_updatebb_4;
// # SUCC: 3 [50.0%] (true,exec) 4 [50.0%] (false,exec)
sha_updatebb_3:
// # PRED: 2 [50.0%] (true,exec)
sha_info->count_hi = sha_info->count_hi + 1;
memAccessCycles += simDCache(sha_info_addr, 0, &csim_result);
// # SUCC: 4 [100.0%] (fallthru,exec)
sha_updatebb_4:
// # PRED: 2 [50.0%] (false,exec) 3 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x4c4, 80, &csim_result);
estimate_power("sha_updatebb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar sha_info at line 338 -- Done
// TODO: UnmappedLS: Load GlobalVar sha_info at line 342 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 344 -- Done
// TODO: UnmappedLS: Load GlobalVar sha_info at line 345 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 347 -- Done
// TODO: UnmappedLS: Load GlobalVar sha_info at line 348 -- Done
// TODO: UnmappedLS: Store GlobalVar sha_info at line 350 -- Done
sha_info->count_lo = D_2787 + sha_info->count_lo;
memAccessCycles += simDCache(sha_info_addr + 20, 0, &csim_result);
memAccessCycles += simDCache(sha_info_addr + 20, 1, &csim_result);
sha_info->count_hi = (count_1 >> 29) + sha_info->count_hi;
memAccessCycles += simDCache(sha_info_addr + 24, 0, &csim_result);
memAccessCycles += simDCache(sha_info_addr + 24, 1, &csim_result);
if (count > 63)
goto sha_updatebb_5;
else
goto sha_updatebb_8;
// # SUCC: 5 [91.0%] (true,exec) 8 [9.0%] (false,exec)
sha_updatebb_5:
// # PRED: 4 [91.0%] (true,exec)
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x514, 16, &csim_result);
estimate_power("sha_updatebb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0x161, 0x164) ? 7 : 0);
D_2795 = &sha_info->data;
D_2795_addr = sha_info_addr + 28;
memAccessCycles += simDCache(sha_info_addr, 1, &csim_result);
ivtmp_232 = 0;
// # SUCC: 6 [100.0%] (fallthru,exec)
sha_updatebb_6:
// # PRED: 6 [91.0%] (true,exec) 5 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Spilling Register
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x524, 44, &csim_result);
estimate_power("sha_updatebb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0x165, 0x16f) ? 7 : 0);
D_3103 = ivtmp_232 + (uintptr_t)buffer;
D_3103_addr = buffer_addr + ivtmp_232;
memAccessCycles += simDCache(buffer_addr, 1, &csim_result);
my_memcpy (D_2795, D_2795_addr, D_3103, D_3103_addr, 64);
sha_transform (sha_info, sha_info_addr);
ivtmp_232 = ivtmp_232 + 64;
if ((int) (count_1 - ivtmp_232) > 63)
goto sha_updatebb_6;
else
goto sha_updatebb_7;
// # SUCC: 6 [91.0%] (true,exec) 7 [9.0%] (false,exec)
sha_updatebb_7:
// # PRED: 6 [9.0%] (false,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x550, 32, &csim_result);
estimate_power("sha_updatebb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0x170, 0x177) ? 7 : 0);
D_3086 = (count_1 + (int)4294967232) / 64;
buffer = (uintptr_t)buffer + (D_3086 + 1) * 64;
memAccessCycles += simDCache(buffer_addr, 0, &csim_result);
D_3089 = count + -64;
count = D_3089 + (int) D_3086 * -64;
// # SUCC: 8 [100.0%] (fallthru,exec)
sha_updatebb_8:
// # PRED: 7 [100.0%] (fallthru,exec) 4 [9.0%] (false,exec)
// Simulating I Cache for obj block 4
memAccessCycles += simICache(0x570, 28, &csim_result);
estimate_power("sha_updatebb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 20 - (enterBlock(0x178, 0x17e) ? 7 : 0);
my_memcpy (&sha_info->data, sha_info_addr, buffer, buffer_addr, (size_t) count);
return;
// # SUCC: EXIT [100.0%]
}
void sha_stream (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsigned char *inData, unsigned long inData_addr, unsigned long int dSize) {
long unsigned int end_289;
long unsigned int end_288;
uintptr_t ivtmp_273;
uintptr_t D_3143;
uintptr_t ivtmp_267;
unsigned char data[8192];
unsigned long data_addr = 0;
long unsigned int count;
long unsigned int end;
long unsigned int start;
long unsigned int j;
unsigned int ARR_SIZE_4;
sha_streambb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x2030;
memAccessCycles += simDCache(0x714, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x60c, 48, &csim_result);
estimate_power("sha_streambb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 23 - (enterBlock(0x1a3, 0x1ae) ? 7 : 0);
ARR_SIZE_4 = ARR_SIZE;
j = ARR_SIZE_4 / 8192;
sha_init (sha_info, sha_info_addr);
if (j != 0)
goto sha_streambb_13;
else
goto sha_streambb_6;
// # SUCC: 13 [91.0%] (true,exec) 6 [9.0%] (false,exec)
sha_streambb_13:
// # PRED: 2 [91.0%] (true,exec)
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x63c, 36, &csim_result);
estimate_power("sha_streambb_13", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0x1af, 0x1b7) ? 7 : 0);
end_289 = 0;
count = 0;
// # SUCC: 3 [100.0%] (fallthru)
sha_streambb_3:
// # PRED: 12 [100.0%] (fallthru) 13 [100.0%] (fallthru)
pipelineCycles += 9 - (enterBlock(0x1b8, 0x1ba) ? 7 : 0);
end_288 = end_289 + 8192;
if (end_288 > end_289)
goto sha_streambb_14;
else
goto sha_streambb_5;
// # SUCC: 14 [99.0%] (true,exec) 5 [1.0%] (false,exec)
sha_streambb_14:
// # PRED: 3 [99.0%] (true,exec)
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x66c, 4, &csim_result);
estimate_power("sha_streambb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 8 - (enterBlock(0x1bb, 0x1bb) ? 7 : 0);
ivtmp_273 = 0;
// # SUCC: 4 [100.0%] (fallthru)
sha_streambb_4:
// # PRED: 4 [99.0%] (true,exec) 14 [100.0%] (fallthru)
// Simulating I Cache for obj block 4
memAccessCycles += simICache(0x670, 24, &csim_result);
estimate_power("sha_streambb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar in_Data at line 445 -- Done
memAccessCycles += simDCache(inData_addr + end_289, 1, &csim_result); // GK
// TODO: UnmappedLS: Inaccurately Matched Store at line 446 -- Done
memAccessCycles += simDCache(SP + data_addr + ivtmp_273, 0, &csim_result); // GK
pipelineCycles += 11 - (enterBlock(0x1bc, 0x1c1) ? 7 : 0);
*(unsigned char*)((uintptr_t)&data + (uintptr_t)ivtmp_273) = *(unsigned char *)((unsigned char *) (end_289 + (uintptr_t)inData) + (uintptr_t)ivtmp_273);
ivtmp_273 = ivtmp_273 + 1;
if (ivtmp_273 != 8192)
goto sha_streambb_4;
else
goto sha_streambb_5;
// # SUCC: 4 [99.0%] (true,exec) 5 [1.0%] (false,exec)
sha_streambb_5:
// # PRED: 4 [1.0%] (false,exec) 3 [1.0%] (false,exec)
// Simulating I Cache for obj block 5
memAccessCycles += simICache(0x688, 32, &csim_result);
estimate_power("sha_streambb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0x1c2, 0x1c9) ? 7 : 0);
sha_update (sha_info, sha_info_addr, data, SP + data_addr, 8192);
count = count + 1;
if (j > count)
goto sha_streambb_12;
else
goto sha_streambb_6;
// # SUCC: 12 [91.0%] (true,exec) 6 [9.0%] (false,exec)
sha_streambb_12:
// # PRED: 5 [91.0%] (true,exec)
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x660, 12, &csim_result);
estimate_power("sha_streambb_12", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
end_289 = end_288;
goto sha_streambb_3;
// # SUCC: 3 [100.0%] (fallthru)
sha_streambb_6:
// # PRED: 5 [9.0%] (false,exec) 2 [9.0%] (false,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
// Simulating I Cache for obj block 6
memAccessCycles += simICache(0x6a8, 12, &csim_result);
estimate_power("sha_streambb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0x1ca, 0x1cc) ? 7 : 0);
if (ARR_SIZE_4 & 8191 != 0)
goto sha_streambb_7;
else
goto sha_streambb_11;
// # SUCC: 7 [61.0%] (true,exec) 11 [39.0%] (false,exec)
sha_streambb_7:
// # PRED: 6 [61.0%] (true,exec)
memAccessCycles += simDCache(0x714, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 7
memAccessCycles += simICache(0x6b4, 20, &csim_result);
estimate_power("sha_streambb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0x1cd, 0x1d1) ? 7 : 0);
start = j * 8192;
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
end = ARR_SIZE;
if (start < end)
goto sha_streambb_8;
else
goto sha_streambb_10;
// # SUCC: 8 [99.0%] (true,exec) 10 [1.0%] (false,exec)
sha_streambb_8:
// # PRED: 7 [99.0%] (true,exec)
// Simulating I Cache for obj block 8
memAccessCycles += simICache(0x6c8, 16, &csim_result);
estimate_power("sha_streambb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0x1d2, 0x1d5) ? 7 : 0);
D_3143 = end - start;
ivtmp_267 = 0;
// # SUCC: 9 [100.0%] (fallthru,exec)
sha_streambb_9:
// # PRED: 9 [99.0%] (true,exec) 8 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + 0x8), 1, &csim_result); // Spilling Register
// Simulating I Cache for obj block 9
memAccessCycles += simICache(0x6d8, 20, &csim_result);
estimate_power("sha_streambb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar in_Data at line 470 -- Done
memAccessCycles += simDCache(inData_addr + start + ivtmp_267, 1, &csim_result); // GK
pipelineCycles += 11 - (enterBlock(0x1d6, 0x1da) ? 7 : 0);
*(unsigned char*)((uintptr_t)&data + (uintptr_t)ivtmp_267) = *(unsigned char *)((uintptr_t)inData + start + (uintptr_t)ivtmp_267);
memAccessCycles += simDCache(inData_addr + (+start+ivtmp_267), 1, &csim_result);
ivtmp_267 = ivtmp_267 + 1;
if (ivtmp_267 != D_3143)
goto sha_streambb_9;
else
goto sha_streambb_10;
// # SUCC: 9 [99.0%] (true,exec) 10 [1.0%] (false,exec)
sha_streambb_10:
// # PRED: 9 [1.0%] (false,exec) 7 [1.0%] (false,exec)
// Simulating I Cache for obj block 10
memAccessCycles += simICache(0x6ec, 16, &csim_result);
estimate_power("sha_streambb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 10 - (enterBlock(0x1db, 0x1de) ? 7 : 0);
sha_update (sha_info, sha_info_addr, &data, SP + data_addr, (int) (end - start));
// # SUCC: 11 [100.0%] (fallthru,exec)
sha_streambb_11:
// # PRED: 6 [39.0%] (false,exec) 10 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 11
memAccessCycles += simICache(0x6fc, 24, &csim_result);
estimate_power("sha_streambb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0x1df, 0x1e4) ? 7 : 0);
sha_final (sha_info, sha_info_addr);
return;
// # SUCC: EXIT [100.0%]
}
instrument/examples/sha/instrumented_power/sha_driver_IR.c 0 → 100644
View file @ d126c154
/***********************************************************
Intermediate representation of
sha/app_dir/sha_driver.c
Converted by ir2c v0.1
***********************************************************/
#include <limits.h>
#include <stdint.h>
#include "ir2c.h"
#include "cacheSim.h"
#include "branchPred.h"
#include "power_estimator.h"
unsigned long SP = 0x1234;
unsigned long long memAccessCycles = 0;
unsigned long long pipelineCycles = 0;
struct csim_result_t csim_result;
/* NIST Secure Hash Algorithm */
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
#include <time.h>
#include "sha.h"
#include "in_small.h"
#include "my_variable.h"
struct SHA_INFO sha_info; //making global
unsigned long sha_info_addr = 0x56770;
int main() {
mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(&csim_result);
branchPred_init();
power_estimator_init();
SP = SP + 0x8;
memAccessCycles += simDCache(0x224, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x228, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x22c, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 36, &csim_result);
estimate_power("mainbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar ARR_SIZE at line 154 -- Done
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result); // GK
pipelineCycles += 16 - (enterBlock(0x96, 0x9e) ? 7 : 0);
sha_stream (&sha_info, sha_info_addr, &in_Data, in_Data_addr, ARR_SIZE);
printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini(&csim_result);
power_estimator_fini();
return 0;
// # SUCC: EXIT [100.0%]
}
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