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hostCompiledSimulation
Commit c2e6278f authored by Gaurav Kukreja's avatar Gaurav Kukreja
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Fixed bugs 

Signed-off-by: Gaurav Kukreja's avatarGaurav Kukreja <gaurav@gauravk.in>
parent 843ff963
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Showing with 37 additions and 28 deletions
cache_simulator/src/genericHwMod.c
View file @ c2e6278f
...@@ -145,7 +145,7 @@ void readConfigFile() ...@@ -145,7 +145,7 @@ void readConfigFile()
// L1 Cache Parameters - same for separate Instruction and Data Cache // L1 Cache Parameters - same for separate Instruction and Data Cache
// L1 Size Params // L1 Size Params
L1Params.cacheSets = 4; L1Params.cacheSets = 4;
L1Params.cacheSizeBytes = 256; L1Params.cacheSizeBytes = 16 * 1024;
L1Params.lineSizeBytes = 16; L1Params.lineSizeBytes = 16;
L1Params.indexLengthBits = log_base2(L1Params.cacheSizeBytes / (L1Params.cacheSets * L1Params.lineSizeBytes)); L1Params.indexLengthBits = log_base2(L1Params.cacheSizeBytes / (L1Params.cacheSets * L1Params.lineSizeBytes));
L1Params.offsetLengthBits = log_base2(L1Params.lineSizeBytes); L1Params.offsetLengthBits = log_base2(L1Params.lineSizeBytes);
...@@ -160,7 +160,7 @@ void readConfigFile() ...@@ -160,7 +160,7 @@ void readConfigFile()
L1Params.cyclesMissFlush = 105; L1Params.cyclesMissFlush = 105;
// L1 Features // L1 Features
L1Params.isWriteThrough = 1; L1Params.isWriteThrough = 0;
// L1 Derived // L1 Derived
L1Params.cacheLength = L1Params.cacheSizeBytes L1Params.cacheLength = L1Params.cacheSizeBytes
...@@ -189,7 +189,7 @@ void readConfigFile() ...@@ -189,7 +189,7 @@ void readConfigFile()
// L2 Cache Parameters - unified cache for data and instruction // L2 Cache Parameters - unified cache for data and instruction
// L2 Size Params // L2 Size Params
L2Params.cacheSets = 8; L2Params.cacheSets = 8;
L2Params.cacheSizeBytes = 2 * 1024; L2Params.cacheSizeBytes = 128 * 1024;
L2Params.lineSizeBytes = 64; L2Params.lineSizeBytes = 64;
L2Params.indexLengthBits = log_base2(L2Params.cacheSizeBytes / (L2Params.cacheSets * L2Params.lineSizeBytes)); L2Params.indexLengthBits = log_base2(L2Params.cacheSizeBytes / (L2Params.cacheSets * L2Params.lineSizeBytes));
L2Params.offsetLengthBits = log_base2(L2Params.lineSizeBytes); L2Params.offsetLengthBits = log_base2(L2Params.lineSizeBytes);
......
cache_simulator/test/cacheSimTest.c
View file @ c2e6278f
...@@ -24,6 +24,7 @@ int main(int argc, char **argv) ...@@ -24,6 +24,7 @@ int main(int argc, char **argv)
{ {
simDCache(address + i, 1); simDCache(address + i, 1);
} }
cacheSimFini(); cacheSimFini();
return 0; return 0;
......
instrument/cacheSimInstrument.py
View file @ c2e6278f
...@@ -86,7 +86,7 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables, ...@@ -86,7 +86,7 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables,
addAnnotationToDict(dictAnnotVarFuncDecl, addAnnotationToDict(dictAnnotVarFuncDecl,
lineNum, lineNum,
annot) annot)
annot_str = "unsigned long memAccessCycles = 0;" annot_str = "unsigned long long memAccessCycles = 0;"
annot = Annotation(annot_str, ISCFileName, lineNum, False) annot = Annotation(annot_str, ISCFileName, lineNum, False)
addAnnotationToDict(dictAnnotVarFuncDecl, addAnnotationToDict(dictAnnotVarFuncDecl,
lineNum, lineNum,
...@@ -333,7 +333,7 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl ...@@ -333,7 +333,7 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl
for i in range(len(blockLSInfo)): for i in range(len(blockLSInfo)):
lsInfo = blockLSInfo.pop(0) lsInfo = blockLSInfo.pop(0)
if lsInfo.isLoad and lsInfo.isPCRelLoad: if lsInfo.isLoad and lsInfo.isPCRelLoad:
annot_str = "memAccessCycles += simICache(0x%x, 4); // PC Relative Load" % (lsInfo.PCRelAdd) annot_str = "memAccessCycles += simDCache(0x%x, 1); // PC Relative Load" % (lsInfo.PCRelAdd)
annot = Annotation(annot_str, funcISC.fileName, blockISC.startLine-1, False) annot = Annotation(annot_str, funcISC.fileName, blockISC.startLine-1, False)
addAnnotationToDict(dictAnnotLoadStore, addAnnotationToDict(dictAnnotLoadStore,
blockISC.startLine-1, blockISC.startLine-1,
...@@ -445,6 +445,9 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl ...@@ -445,6 +445,9 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl
annot_str = 'printf("memAccessCycles = \%llu\\n", memAccessCycles);' annot_str = 'printf("memAccessCycles = \%llu\\n", memAccessCycles);'
annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False) annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False)
addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot) addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot)
annot_str = 'cacheSimFini();'
annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False)
addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot)
break break
else: else:
continue continue
......
instrument/examples/adpcm/instrumented/adpcm_IR.c
View file @ c2e6278f
...@@ -115,7 +115,7 @@ SP = SP + 0x30; ...@@ -115,7 +115,7 @@ SP = SP + 0x30;
memAccessCycles += simDCache((SP + 0x4), 1); // Spilling Register memAccessCycles += simDCache((SP + 0x4), 1); // Spilling Register
memAccessCycles += simDCache((SP + 0xc), 1); // Spilling Register memAccessCycles += simDCache((SP + 0xc), 1); // Spilling Register
memAccessCycles += simDCache((SP + 0xc), 1); // Reading Spilt Register memAccessCycles += simDCache((SP + 0xc), 1); // Reading Spilt Register
memAccessCycles += simICache(0x4a8, 4); // PC Relative Load memAccessCycles += simDCache(0x4a8, 1); // PC Relative Load
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x36c, 44); memAccessCycles += simICache(0x36c, 44);
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247 // TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247
...@@ -134,7 +134,7 @@ memAccessCycles += simICache(0x36c, 44); ...@@ -134,7 +134,7 @@ memAccessCycles += simICache(0x36c, 44);
adpcm_coderbb_3: adpcm_coderbb_3:
// # PRED: 2 [91.0%] (true,exec) // # PRED: 2 [91.0%] (true,exec)
memAccessCycles += simICache(0x4a8, 4); // PC Relative Load memAccessCycles += simDCache(0x4a8, 1); // PC Relative Load
memAccessCycles += simDCache((SP + outp_addr), 0); memAccessCycles += simDCache((SP + outp_addr), 0);
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x398, 32); memAccessCycles += simICache(0x398, 32);
......
instrument/examples/adpcm/instrumented/my_ctop_IR.c
View file @ c2e6278f
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#include "ir2c.h" #include "ir2c.h"
#include "cacheSim.h" #include "cacheSim.h"
unsigned long SP = 0x1234; unsigned long SP = 0x1234;
unsigned long memAccessCycles = 0; unsigned long long memAccessCycles = 0;
/* /*
** Timing - Test timing on adpcm coder and decoder. ** Timing - Test timing on adpcm coder and decoder.
...@@ -63,8 +63,8 @@ mainbb_2: ...@@ -63,8 +63,8 @@ mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec) // # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(); cacheSimInit();
SP = SP + 0x30; SP = SP + 0x30;
memAccessCycles += simICache(0x354, 4); // PC Relative Load memAccessCycles += simDCache(0x354, 1); // PC Relative Load
memAccessCycles += simICache(0x358, 4); // PC Relative Load memAccessCycles += simDCache(0x358, 1); // PC Relative Load
memAccessCycles += simDCache(ARR_SIZE_addr, 1); memAccessCycles += simDCache(ARR_SIZE_addr, 1);
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0); memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0);
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
...@@ -79,11 +79,11 @@ memAccessCycles += simICache(0x200, 36); ...@@ -79,11 +79,11 @@ memAccessCycles += simICache(0x200, 36);
mainbb_14: mainbb_14:
// # PRED: 2 [91.0%] (true,exec) // # PRED: 2 [91.0%] (true,exec)
memAccessCycles += simICache(0x35c, 4); // PC Relative Load memAccessCycles += simDCache(0x35c, 1); // PC Relative Load
memAccessCycles += simDCache((SP + 0x4), 1); // Spilling Register memAccessCycles += simDCache((SP + 0x4), 1); // Spilling Register
memAccessCycles += simICache(0x360, 4); // PC Relative Load memAccessCycles += simDCache(0x360, 1); // PC Relative Load
memAccessCycles += simICache(0x364, 4); // PC Relative Load memAccessCycles += simDCache(0x364, 1); // PC Relative Load
memAccessCycles += simICache(0x368, 4); // PC Relative Load memAccessCycles += simDCache(0x368, 1); // PC Relative Load
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x224, 40); memAccessCycles += simICache(0x224, 40);
end_43 = 0; end_43 = 0;
...@@ -147,7 +147,7 @@ memAccessCycles += simICache(0x24c, 12); ...@@ -147,7 +147,7 @@ memAccessCycles += simICache(0x24c, 12);
mainbb_7: mainbb_7:
// # PRED: 6 [9.0%] (false,exec) 2 [9.0%] (false,exec) // # PRED: 6 [9.0%] (false,exec) 2 [9.0%] (false,exec)
memAccessCycles += simICache(0x358, 4); // PC Relative Load memAccessCycles += simDCache(0x358, 1); // PC Relative Load
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1); memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1);
// Simulating I Cache for obj block 6 // Simulating I Cache for obj block 6
memAccessCycles += simICache(0x2b8, 32); memAccessCycles += simICache(0x2b8, 32);
...@@ -159,7 +159,7 @@ memAccessCycles += simICache(0x2b8, 32); ...@@ -159,7 +159,7 @@ memAccessCycles += simICache(0x2b8, 32);
mainbb_8: mainbb_8:
// # PRED: 7 [61.0%] (true,exec) // # PRED: 7 [61.0%] (true,exec)
memAccessCycles += simICache(0x354, 4); // PC Relative Load memAccessCycles += simDCache(0x354, 1); // PC Relative Load
// Simulating I Cache for obj block 7 // Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2d8, 24); memAccessCycles += simICache(0x2d8, 24);
start_40 = j * 10240; start_40 = j * 10240;
...@@ -173,8 +173,8 @@ memAccessCycles += simICache(0x2d8, 24); ...@@ -173,8 +173,8 @@ memAccessCycles += simICache(0x2d8, 24);
mainbb_9: mainbb_9:
// # PRED: 8 [99.0%] (true,exec) // # PRED: 8 [99.0%] (true,exec)
memAccessCycles += simICache(0x35c, 4); // PC Relative Load memAccessCycles += simDCache(0x35c, 1); // PC Relative Load
memAccessCycles += simICache(0x360, 4); // PC Relative Load memAccessCycles += simDCache(0x360, 1); // PC Relative Load
// Simulating I Cache for obj block 8 // Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2f0, 28); memAccessCycles += simICache(0x2f0, 28);
i = (int) start_40; i = (int) start_40;
...@@ -201,9 +201,9 @@ memAccessCycles += simICache(0x30c, 36); ...@@ -201,9 +201,9 @@ memAccessCycles += simICache(0x30c, 36);
mainbb_11: mainbb_11:
// # PRED: 10 [1.0%] (false,exec) 8 [1.0%] (false,exec) // # PRED: 10 [1.0%] (false,exec) 8 [1.0%] (false,exec)
memAccessCycles += simICache(0x360, 4); // PC Relative Load memAccessCycles += simDCache(0x360, 1); // PC Relative Load
memAccessCycles += simICache(0x364, 4); // PC Relative Load memAccessCycles += simDCache(0x364, 1); // PC Relative Load
memAccessCycles += simICache(0x368, 4); // PC Relative Load memAccessCycles += simDCache(0x368, 1); // PC Relative Load
// Simulating I Cache for obj block 10 // Simulating I Cache for obj block 10
memAccessCycles += simICache(0x330, 20); memAccessCycles += simICache(0x330, 20);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr); adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr);
...@@ -214,6 +214,7 @@ mainbb_12: ...@@ -214,6 +214,7 @@ mainbb_12:
// Simulating I Cache for obj block 11 // Simulating I Cache for obj block 11
memAccessCycles += simICache(0x344, 16); memAccessCycles += simICache(0x344, 16);
printf("memAccessCycles = \%llu\n", memAccessCycles); printf("memAccessCycles = \%llu\n", memAccessCycles);
cacheSimFini();
return 0; return 0;
// # SUCC: EXIT [100.0%] // # SUCC: EXIT [100.0%]
......
instrument/examples/sieve/instrumented/erat_sieve_no_print_IR.c
View file @ c2e6278f
...@@ -10,7 +10,7 @@ ...@@ -10,7 +10,7 @@
#include "ir2c.h" #include "ir2c.h"
#include "cacheSim.h" #include "cacheSim.h"
unsigned long SP = 0x1234; unsigned long SP = 0x1234;
unsigned long memAccessCycles = 0; unsigned long long memAccessCycles = 0;
#include <stdio.h> #include <stdio.h>
...@@ -23,7 +23,7 @@ struct test { ...@@ -23,7 +23,7 @@ struct test {
unsigned int v; unsigned int v;
unsigned int k; unsigned int k;
} m = { 1, 1 }; } m = { 1, 1 };
unsigned long m_addr; unsigned long m_addr = 0x7c8;
void sieve_func() { void sieve_func() {
int j_76; int j_76;
...@@ -44,7 +44,8 @@ void sieve_func() { ...@@ -44,7 +44,8 @@ void sieve_func() {
sieve_funcbb_2: sieve_funcbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec) // # PRED: ENTRY [100.0%] (fallthru,exec)
memAccessCycles += simICache(0x35c, 4); // PC Relative Load SP = SP + 0x1e84a0;
memAccessCycles += simDCache(0x35c, 4); // PC Relative Load
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 40); memAccessCycles += simICache(0x200, 40);
ivtmp_68 = 0; ivtmp_68 = 0;
...@@ -134,7 +135,7 @@ memAccessCycles += simICache(0x2c0, 24); ...@@ -134,7 +135,7 @@ memAccessCycles += simICache(0x2c0, 24);
sieve_funcbb_8: sieve_funcbb_8:
// # PRED: 7 [1.0%] (false,exec) // # PRED: 7 [1.0%] (false,exec)
memAccessCycles += simICache(0x35c, 4); // PC Relative Load memAccessCycles += simDCache(0x35c, 4); // PC Relative Load
// Simulating I Cache for obj block 8 // Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2d8, 24); memAccessCycles += simICache(0x2d8, 24);
j = 2; j = 2;
...@@ -171,7 +172,7 @@ memAccessCycles += simICache(0x2f0, 28); ...@@ -171,7 +172,7 @@ memAccessCycles += simICache(0x2f0, 28);
sieve_funcbb_12: sieve_funcbb_12:
// # PRED: 11 [1.0%] (false,exec) // # PRED: 11 [1.0%] (false,exec)
memAccessCycles += simICache(0x35c, 4); // PC Relative Load memAccessCycles += simDCache(0x35c, 4); // PC Relative Load
memAccessCycles += simDCache(results_addr + (4 * (0)), 1); memAccessCycles += simDCache(results_addr + (4 * (0)), 1);
// Simulating I Cache for obj block 10 // Simulating I Cache for obj block 10
memAccessCycles += simICache(0x30c, 16); memAccessCycles += simICache(0x30c, 16);
...@@ -194,6 +195,7 @@ sieve_funcbb_14: ...@@ -194,6 +195,7 @@ sieve_funcbb_14:
// Simulating I Cache for obj block 12 // Simulating I Cache for obj block 12
memAccessCycles += simICache(0x328, 12); memAccessCycles += simICache(0x328, 12);
// TODO: UnmappedLS: Load GlobalVar results at line 224 // TODO: UnmappedLS: Load GlobalVar results at line 224
memAccessCycles += simDCache(results_addr + ivtmp_36 - (D_2230 - 1999996), 1);
if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0) if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0)
goto sieve_funcbb_16; goto sieve_funcbb_16;
else else
...@@ -213,7 +215,7 @@ memAccessCycles += simICache(0x334, 12); ...@@ -213,7 +215,7 @@ memAccessCycles += simICache(0x334, 12);
sieve_funcbb_16: sieve_funcbb_16:
// # PRED: 14 [4.5%] (true,exec) 15 [1.1%] (false,exec) 12 [4.5%] (true,exec) // # PRED: 14 [4.5%] (true,exec) 15 [1.1%] (false,exec) 12 [4.5%] (true,exec)
memAccessCycles += simICache(0x360, 4); // PC Relative Load memAccessCycles += simDCache(0x360, 4); // PC Relative Load
memAccessCycles += simDCache(m_addr, 0); memAccessCycles += simDCache(m_addr, 0);
// Simulating I Cache for obj block 14 // Simulating I Cache for obj block 14
memAccessCycles += simICache(0x340, 28); memAccessCycles += simICache(0x340, 28);
...@@ -229,10 +231,12 @@ int main (void) { ...@@ -229,10 +231,12 @@ int main (void) {
mainbb_2: mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec) // # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(); cacheSimInit();
SP = SP + 0x8;
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x364, 20); memAccessCycles += simICache(0x364, 20);
sieve_func (); sieve_func ();
printf("memAccessCycles = \%lu\n", memAccessCycles); printf("memAccessCycles = \%llu\n", memAccessCycles);
cacheSimFini();
return 0; return 0;
// # SUCC: EXIT [100.0%] // # SUCC: EXIT [100.0%]
......
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