Adding missed increment SP annotation at beginning of function

Signed-off-by: Gaurav Kukreja <gaurav@gauravk.in>

instrument/cacheSimInstrument.py

@@ -317,8 +317,12 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl
             annot_str = "cacheSimInit();"
             annot = Annotation(annot_str, funcISC.fileName, funcISC.cfg.listBlocks[0].startLine-1, False)
             addAnnotationToDict(dictAnnotLoadStore, funcISC.cfg.listBlocks[0].startLine-1, annot)
-        
+            
         funcObj = find(lambda fn: fn.functionName == funcISC.functionName, listObjdumpFunctions)
+        annot_str = "SP = SP + 0x%x;" % (funcObj.stackSize)
+        annot = Annotation(annot_str, funcISC.fileName, funcISC.cfg.listBlocks[0].startLine-1, False)
+        addAnnotationToDict(dictAnnotLoadStore, funcISC.cfg.listBlocks[0].startLine-1, annot)
+        
         for blockObj in funcObj.cfg.listBlocks:
             mappedBlocksISCInd = blockObj.mapsTo
             blockLSInfo = findLoadStoreBetweenLines(listLSInfo, blockObj.startLine, blockObj.endLine)

instrument/examples/adpcm/instrumented/adpcm_IR.c

@@ -111,6 +111,7 @@ void  adpcm_coder (short indata[], unsigned long indata_addr, char outdata[], un
 
 adpcm_coderbb_2:
 //  # PRED: ENTRY [100.0%]  (fallthru,exec)
+SP = SP + 0x30;
 memAccessCycles += simDCache((SP + 0x4), 1);  // Spilling Register
 memAccessCycles += simDCache((SP + 0xc), 1);  // Spilling Register
 memAccessCycles += simDCache((SP + 0xc), 1);  // Reading Spilt Register

instrument/examples/adpcm/instrumented/my_ctop_IR.c

@@ -62,6 +62,7 @@ int main() {
 mainbb_2:
 //  # PRED: ENTRY [100.0%]  (fallthru,exec)
 cacheSimInit();
+SP = SP + 0x30;
 memAccessCycles += simICache(0x354, 4);  // PC Relative Load
 memAccessCycles += simICache(0x358, 4);  // PC Relative Load
 memAccessCycles += simDCache(ARR_SIZE_addr, 1);