Cache Simulator

Signed-off-by: Gaurav Kukreja <gaurav@gauravk.in>

cache_simulator/.gitignore

+/Debug

cache_simulator/.project

+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>cache_simulator</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
+</projectDescription>

cache_simulator/Makefile

+# Makefile for cache simulator
+
+include Makefile.macros
+
+check:
+	$(MAKE) -C $(SRC_DIR) TARGET_DIR=$(TEST_DIR) all
+	$(MAKE) -C $(TEST_DIR) all
+	$(TEST_DIR)/cacheSimTest
+
+check_clean:
+	$(MAKE) -C $(TEST_DIR) clean
\ No newline at end of file

cache_simulator/Makefile.macros

+# Configuration for cache simulator
+
+# Path to Cache Simulator
+CSIM_DIR = /home/gaurav/eclipse-workspace/sls_thesis_project/cache_simulator
+
+# No need to change
+SRC_DIR = $(CSIM_DIR)/src
+TEST_DIR = $(CSIM_DIR)/test
+
+# Hardware Model to use
+CACHESIM_HWMOD = generic
+
+# Cache Simulation Source Code
+SOURCES=cacheSim.c cacheSim.h cacheSimStat.c cacheSimStat.h cacheSimHwMod.h
+
+# Add the source file(s) for the cache simulator hardware models
+ifeq ($(CACHESIM_HWMOD),generic)
+    SOURCES += genericHwMod.c
+endif
\ No newline at end of file

cache_simulator/src/Makefile

+
+
+include ../Makefile.macros
+
+# Default Target directory to install cache simulator. Will be over-rided.
+TARGET_DIR = ../test
+
+CP = cp
+
+all:
+	$(CP) $(SOURCES) $(TARGET_DIR)	
\ No newline at end of file

cache_simulator/src/cacheSim.c

+/**
+ * cache_sim.c
+ * Purpose: This is a cache simulation software. The benchmark code is
+ * instrumented, and the modified code is compiled with the simulator. The
+ * cache organization can be configured from human-readable config files.
+ *
+ * @author Gaurav Kukreja
+ */
+
+#include <stdio.h>
+#include "cacheSimHwMod.h"
+#include "cacheSimStat.h"
+
+#define COLLECT_STAT
+
+#define HERE printf("%s: %s: %d\n", __FILE__, __func__, __LINE__)
+
+/******************************************************************************
+ * GLOBAL VARIABLES
+ ******************************************************************************/
+
+
+/******************************************************************************
+ * DATA STRUCTURES
+ ******************************************************************************/
+
+
+/******************************************************************************
+ * LOCAL FUNCTION DECLARATIONS
+ ******************************************************************************/
+
+
+/******************************************************************************
+ * LOCAL FUNCTIONS
+ ******************************************************************************/
+
+
+/******************************************************************************
+ * GLOBAL FUNCTIONS
+ ******************************************************************************/
+
+/**
+ * Simulates Instruction Cache access by benchmark
+ *
+ * @param address Starting address of instructions in the basic block
+ * @param nBytes Number of bytes of instructions accessed in the basic block
+ *
+ * @return number of clock cycles spent
+ */
+unsigned int simICache(unsigned long address, unsigned int nBytes)
+{
+	unsigned int nCycles;
+	cacheSimStat.access_type = ACCESS_TYPE_INVALID;
+	cacheSimStat.nCycles = 0;
+	cacheSimStat.powerMicroJ = 0;
+
+	nCycles = hwMod.simICache(address, nBytes);
+
+#ifdef COLLECT_STAT
+	cacheSimStatCollect();
+#endif
+
+	return nCycles;
+}
+
+/**
+ * Simulates Data Cache access by benchmark
+ *
+ * @param address Address of data accessed
+ *
+ * @return number of clock cycles spent
+ */
+unsigned int simDCache(unsigned long address, unsigned int isReadAccess)
+{
+	unsigned int nCycles;
+	cacheSimStat.access_type = ACCESS_TYPE_INVALID;
+	cacheSimStat.nCycles = 0;
+	cacheSimStat.powerMicroJ = 0;
+
+	nCycles = hwMod.simDCache(address, isReadAccess);
+
+#ifdef COLLECT_STAT
+	cacheSimStatCollect();
+#endif
+
+	return nCycles;
+}
+
+/**
+ * Initialize the cache data structures
+ */
+void cacheSimInit()
+{
+	hwMod.cacheSimInit();
+}
+
+/**
+ * Frees data structures and cleans up
+ */
+void cacheSimFini()
+{
+	hwMod.cacheSimFini();
+
+#ifdef COLLECT_STAT
+	cacheSimStatPrint();
+#endif
+}

cache_simulator/src/cacheSim.h

+/**
+ * cache_sim.h
+ * Purpose: Interface to the cache simulator. Defines functions that will be
+ * called from the benchmark.
+ *
+ * @author: Gaurav Kukreja
+ */
+
+#ifndef CACHE_SIM_H
+#define CACHE_SIM_H
+
+/**
+ * Simulates Instruction Cache access by benchmark
+ *
+ * @param address Starting address of instructions in the basic block
+ * @param nBytes Number of bytes of instructions accessed in the basic block
+ *
+ * @return number of clock cycles spent
+ */
+unsigned int simICache(unsigned long address, unsigned int nBytes);
+
+/**
+ * Simulates Data Cache access by benchmark
+ *
+ * @param address Address of data accessed
+ * @param isReadAccess Tells cache simulator if it was read access.
+ *
+ * @return number of clock cycles spent
+ */
+unsigned int simDCache(unsigned long address, unsigned int isReadAccess);
+
+/**
+ * Initialize the cache data structures
+ */
+void cacheSimInit();
+
+/**
+ * Frees data structures and cleans up
+ *
+ */
+void cacheSimFini();
+
+#endif // CACHE_SIM_H

cache_simulator/src/cacheSimHwMod.h

+/**
+ * cacheSimHwMod.h
+ * Purpose: Contains the Hardware Model Descriptor Data Structure
+ *
+ * @author: Gaurav Kukreja
+ */
+
+#ifndef CACHE_SIM_HW_MOD_H
+#define CACHE_SIM_HW_MOD_H
+
+#include "cacheSimStat.h"
+
+/**
+ * Cache Simulation Hardware Model Descriptor
+ */
+struct cacheSimHwMod_t
+{
+	/**
+	 * Simulates Instruction Cache access by benchmark
+	 *
+	 * @param address Starting address of instructions in the basic block
+	 * @param nBytes Number of bytes of instructions accessed in the basic block
+	 *
+	 * @return number of clock cycles spent
+	 */
+	unsigned int (*simICache) (unsigned long address, unsigned int nBytes);
+
+	/**
+	 * Simulates Data Cache access by benchmark
+	 *
+	 * @param address Address of data accessed
+	 * @param isReadAccess Tells cache simulator if it was read access.
+	 *
+	 * @return number of clock cycles spent
+	 */
+	unsigned int (*simDCache) (unsigned long address, unsigned int isReadAccess);
+
+	/**
+	 * Initialize the cache data structures
+	 *
+	 * @param configFile Path to the json config file which describes cache
+	 *        organization
+	 */
+	void (*cacheSimInit) ();
+
+	/**
+	 * Frees data structures and cleans up
+	 */
+	void (*cacheSimFini) ();
+};
+
+
+/**
+ * The hwMod data structure is a global data structure which will be defined in
+ * the hardware model implementations. It will be accessed from cacheSim.c by
+ * including this file, and be linked to the specific hardware model at compile
+ * time.
+ */
+extern struct cacheSimHwMod_t hwMod;
+
+#endif // CACHE_SIM_HW_MOD_H

cache_simulator/src/cacheSimStat.c

+/**
+ * cacheSimStat.c
+ * Purpose: This code basically collects the results from cache simulation,
+ * and records the statistics for reporting later.
+ */
+
+#include <stdio.h>
+#include "cacheSimStat.h"
+
+/**
+ * Global Variable used to receive simulation statistics from HW Model
+ * Implementation.
+ */
+struct cacheSimStat_t cacheSimStat;
+
+static unsigned long nAccesses = 0;
+static unsigned long nL1Miss = 0;
+static unsigned long nL1Hit = 0;
+static unsigned long nL2Hit = 0;
+static unsigned long nL2Miss = 0;
+
+void cacheSimStatCollect()
+{
+	nAccesses++;
+	switch(cacheSimStat.access_type)
+	{
+		case L1_HIT_READ:
+		case L1_HIT_WRITEBACK:
+		case L1_HIT_WRITETHROUGH:
+			nL1Hit++;
+			break;
+		case L1_MISS:
+		case L1_MISS_FLUSH:
+			nL1Miss++;
+			break;
+		case L2_HIT_READ:
+		case L2_HIT_WRITEBACK:
+		case L2_HIT_WRITETHROUGH:
+			nL1Miss++;
+			nL2Hit++;
+			break;
+		case L2_MISS:
+		case L2_MISS_FLUSH:
+			nL1Miss++;
+			nL2Miss++;
+			break;
+		default:
+			break;
+	}
+}
+
+void cacheSimStatPrint()
+{
+	printf("Accesses = %lu \n"
+			"L1 Hits = %lu \n"
+			"L1 Miss = %lu (L1 Miss Rate = %lu) \n"
+			"L2 Hits = %lu \n"
+			"L2 Miss = %lu (L2 Miss Rate = %lu) \n",
+			nAccesses, nL1Hit, nL1Miss, nL1Miss*100/nAccesses,
+			nL2Hit, nL2Miss, nL2Miss*100/nAccesses);
+}
+

cache_simulator/src/cacheSimStat.h

+/**
+ * cacheSimStat.h
+ * Purpose: Data structures and function declarations for collecting statistics
+ * returned from Cache Simulation.
+ */
+
+#ifndef CACHE_SIM_STAT_H
+#define CACHE_SIM_STAT_H
+
+/**
+ * Enum to specify the kind of memory access.
+ */
+enum cacheSimStatAccess_t
+{
+	ACCESS_TYPE_INVALID = 0,
+	L1_HIT_READ,
+	L1_HIT_WRITEBACK,
+	L1_HIT_WRITETHROUGH,
+	L1_MISS_FLUSH,
+	L1_MISS,
+	L2_HIT_READ,
+	L2_HIT_WRITEBACK,
+	L2_HIT_WRITETHROUGH,
+	L2_MISS_FLUSH,
+	L2_MISS
+};
+
+
+/**
+ * Statistics will be returned by Hardware Model Implementation of the cache.
+ */
+struct cacheSimStat_t
+{
+	enum cacheSimStatAccess_t access_type;
+	unsigned int nCycles;
+	unsigned int powerMicroJ;
+};
+
+/**
+ * cacheSimStat is globally declared in cacheSim.c. The Hardware Model
+ * implementation will use this data structure to return the cache simulation
+ * statistics.
+ */
+extern struct cacheSimStat_t cacheSimStat;
+
+void cacheSimStatCollect();
+
+void cacheSimStatPrint();
+
+#endif // CACHE_SIM_STAT_H

cache_simulator/test/Makefile

+include ../Makefile.macros
+
+CC=gcc
+CFLAGS=-O2 -std=c99
+
+TEST_SOURCES = cacheSimTest.c
+
+all: cacheSimTest
+
+cacheSimTest: $(SOURCES) $(TEST_SOURCES)
+	$(CC) $(CFLAGS) -o $@ $^
+
+clean: 
+	rm -rf *.o cacheSimTest 
+	for f in $(SOURCES); do \
+		rm -rf $$f; \
+	done
\ No newline at end of file

cache_simulator/test/cacheSimTest.c

+/**
+ * This program tests the cache simulation software. It basically generates a
+ * number of memory accesses, and checks the statistics generated from cache
+ * simulation.
+ */
+
+#include "cacheSim.h"
+
+#define HERE printf("%s: %s: %d\n", __FILE__, __func__, __LINE__)
+
+#define MAX_REPEATS 2
+#define MAX_ACCESSES 524288
+
+#define START_ADD 0x12345678
+
+int main(int argc, char **argv)
+{
+	unsigned long address = START_ADD;
+
+	cacheSimInit();
+
+	for(unsigned long j = 0; j < MAX_REPEATS; j++)
+		for(unsigned long i = 0; i < MAX_ACCESSES; i++)
+		{
+			simDCache(address + i, 1);
+		}
+	cacheSimFini();
+
+	return 0;
+}