Intermediate changes in cacheSim, probably won't compile

Signed-off-by: Gaurav Kukreja <gaurav@gauravk.in>

cache_simulator/headers/cacheSim.h

@@ -17,7 +17,7 @@
  *
  * @return number of clock cycles spent
  */
-extern unsigned int simICache(unsigned long address, unsigned int nBytes);
+extern unsigned long simICache(unsigned long address, unsigned int nBytes);
 
 /**
  * Simulates Data Cache access by benchmark
@@ -27,7 +27,7 @@ extern unsigned int simICache(unsigned long address, unsigned int nBytes);
  *
  * @return number of clock cycles spent
  */
-extern unsigned int simDCache(unsigned long address, unsigned int isReadAccess);
+extern unsigned long simDCache(unsigned long address, unsigned int isReadAccess);
 
 /**
  * Initialize the cache data structures

cache_simulator/src/cacheSim.c

@@ -47,7 +47,7 @@
  *
  * @return number of clock cycles spent
  */
-unsigned int simICache(unsigned long address, unsigned int nBytes)
+unsigned long simICache(unsigned long address, unsigned int nBytes)
 {
 	unsigned int nCycles;
 	cacheSimStat.access_type = ACCESS_TYPE_INVALID;
@@ -70,7 +70,7 @@ unsigned int simICache(unsigned long address, unsigned int nBytes)
  *
  * @return number of clock cycles spent
  */
-unsigned int simDCache(unsigned long address, unsigned int isReadAccess)
+unsigned long simDCache(unsigned long address, unsigned int isReadAccess)
 {
 	unsigned int nCycles;
 	cacheSimStat.access_type = ACCESS_TYPE_INVALID;

cache_simulator/src/cacheSimHwMod.h

@@ -23,7 +23,7 @@ struct cacheSimHwMod_t
 	 *
 	 * @return number of clock cycles spent
 	 */
-	unsigned int (*simICache) (unsigned long address, unsigned int nBytes);
+	unsigned long (*simICache) (unsigned long address, unsigned int nBytes);
 
 	/**
 	 * Simulates Data Cache access by benchmark
@@ -33,7 +33,7 @@ struct cacheSimHwMod_t
 	 *
 	 * @return number of clock cycles spent
 	 */
-	unsigned int (*simDCache) (unsigned long address, unsigned int isReadAccess);
+	unsigned long (*simDCache) (unsigned long address, unsigned int isReadAccess);
 
 	/**
 	 * Initialize the cache data structures

cache_simulator/src/genericHwMod.c

@@ -96,6 +96,7 @@ struct cacheLine_t
 
 struct cacheParam_t L1Params;
 struct cacheParam_t L2Params;
+
 struct cacheLine_t **L1DCache;
 struct cacheLine_t **L1ICache;
 struct cacheLine_t **L2DCache;
@@ -458,7 +459,7 @@ unsigned int generic_simL1ICache(unsigned long address,
  *
  * @return number of clock cycles spent
  */
-unsigned int generic_simICache(unsigned long address, unsigned int nBytes)
+unsigned long generic_simICache(unsigned long address, unsigned int nBytes)
 {
 	unsigned int nCycles = 100;
 
@@ -659,7 +660,7 @@ unsigned int generic_simL1DCache(unsigned long address,
  *
  * @return number of clock cycles spent
  */
-unsigned int generic_simDCache(unsigned long address, unsigned int isReadAccess)
+unsigned long generic_simDCache(unsigned long address, unsigned int isReadAccess)
 {
 	unsigned int nCycles = 100;
 	unsigned int ret;