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hostCompiledSimulation
Commit 4c4e8d5e authored by Gaurav Kukreja's avatar Gaurav Kukreja
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Power, somehow working. Results 

Signed-off-by: Gaurav Kukreja's avatarGaurav Kukreja <gaurav@gauravk.in>
parent c27a2775
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instrument/examples/adpcm/instrumented/Makefile
View file @ 4c4e8d5e
include ../../../../cache_simulator/Makefile.macros include ../../../../cache_simulator/Makefile.macros
include ../../../../branch_predictor/Makefile.macros include ../../../../branch_predictor/Makefile.macros
include ../../../../power_estimator/Makefile.macros
CC = gcc CC = gcc
CFLAGS = -O2 -std=c99 CFLAGS = -O2 -std=c99
INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS) INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS) -I$(POWEREST_HEADERS)
LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB) LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB) -L$(POWEREST_LIB)
APP_SOURCES = my_ctop_IR.c adpcm_IR.c APP_SOURCES = my_ctop_IR.c adpcm_IR.c
all: my_ctop_IR.out all: my_ctop_IR.out
my_ctop_IR.out: $(APP_SOURCES) my_ctop_IR.out: $(APP_SOURCES)
$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred $(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred -lpowerEst
check: my_ctop_IR.out check: my_ctop_IR.out
export LD_LIBRARY_PATH=$(CACHESIM_LIB) export LD_LIBRARY_PATH=$(CACHESIM_LIB)
......
instrument/examples/adpcm/instrumented/adpcm_IR.c
View file @ 4c4e8d5e
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#include "ir2c.h" #include "ir2c.h"
#include "cacheSim.h" #include "cacheSim.h"
#include "branchPred.h" #include "branchPred.h"
#include "power_estimator.h"
extern unsigned long SP; extern unsigned long SP;
extern unsigned long long memAccessCycles; extern unsigned long long memAccessCycles;
extern unsigned long long pipelineCycles; extern unsigned long long pipelineCycles;
...@@ -121,6 +122,7 @@ memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Reg ...@@ -121,6 +122,7 @@ memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Reg
memAccessCycles += simDCache(0x4a8, 1, &csim_result); // PC Relative Load memAccessCycles += simDCache(0x4a8, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x36c, 44, &csim_result); memAccessCycles += simICache(0x36c, 44, &csim_result);
estimate_power("adpcm_coderbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247 // TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 249 // TODO: UnmappedLS: Load GlobalVar coder_1_state at line 249
pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 7 : 0); pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 7 : 0);
...@@ -142,6 +144,7 @@ memAccessCycles += simDCache(0x4a8, 1, &csim_result); // PC Relative Load ...@@ -142,6 +144,7 @@ memAccessCycles += simDCache(0x4a8, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result); memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x398, 32, &csim_result); memAccessCycles += simICache(0x398, 32, &csim_result);
estimate_power("adpcm_coderbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0); pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
outp = outdata; outp = outdata;
// memAccessCycles += simDCache(outdata_addr, 1, &csim_result); // memAccessCycles += simDCache(outdata_addr, 1, &csim_result);
...@@ -283,6 +286,7 @@ adpcm_coderbb_18: ...@@ -283,6 +286,7 @@ adpcm_coderbb_18:
// # PRED: 16 [100.0%] (fallthru,exec) 17 [100.0%] (fallthru,exec) // # PRED: 16 [100.0%] (fallthru,exec) 17 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 2 // Simulating I Cache for obj block 2
memAccessCycles += simICache(0x3b8, 200, &csim_result); memAccessCycles += simICache(0x3b8, 200, &csim_result);
estimate_power("adpcm_coderbb_18", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar pcmdata at line 263 // TODO: UnmappedLS: Load GlobalVar pcmdata at line 263
// TODO: UnmappedLS: Load LocalVar outp at line 305 // TODO: UnmappedLS: Load LocalVar outp at line 305
// TODO: UnmappedLS: Store GlobalVar pcmdata at line 306 // TODO: UnmappedLS: Store GlobalVar pcmdata at line 306
...@@ -314,6 +318,7 @@ adpcm_coderbb_21: ...@@ -314,6 +318,7 @@ adpcm_coderbb_21:
// # PRED: 19 [33.0%] (false,exec) 20 [100.0%] (fallthru,exec) 2 [9.0%] (false,exec) // # PRED: 19 [33.0%] (false,exec) 20 [100.0%] (fallthru,exec) 2 [9.0%] (false,exec)
// Simulating I Cache for obj block 3 // Simulating I Cache for obj block 3
memAccessCycles += simICache(0x480, 16, &csim_result); memAccessCycles += simICache(0x480, 16, &csim_result);
estimate_power("adpcm_coderbb_21", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load LocalVar outp at line 314 // TODO: UnmappedLS: Load LocalVar outp at line 314
// TODO: UnmappedLS: Store GlobalVar stepsizeTable at line 315 // TODO: UnmappedLS: Store GlobalVar stepsizeTable at line 315
memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Register memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Register
......
instrument/examples/adpcm/instrumented/my_ctop_IR.c
View file @ 4c4e8d5e
...@@ -69,6 +69,7 @@ mainbb_2: ...@@ -69,6 +69,7 @@ mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec) // # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(&csim_result); cacheSimInit(&csim_result);
branchPred_init(); branchPred_init();
power_estimator_init();
SP = SP + 0x30; SP = SP + 0x30;
memAccessCycles += simDCache(0x354, 1, &csim_result); // PC Relative Load memAccessCycles += simDCache(0x354, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x358, 1, &csim_result); // PC Relative Load memAccessCycles += simDCache(0x358, 1, &csim_result); // PC Relative Load
...@@ -76,6 +77,7 @@ memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result); ...@@ -76,6 +77,7 @@ memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0, &csim_result); memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0, &csim_result);
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 36, &csim_result); memAccessCycles += simICache(0x200, 36, &csim_result);
estimate_power("mainbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 7 : 0); pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 7 : 0);
ARR_SIZE_0 = ARR_SIZE; ARR_SIZE_0 = ARR_SIZE;
j = ARR_SIZE_0 / 10240; j = ARR_SIZE_0 / 10240;
...@@ -94,6 +96,7 @@ memAccessCycles += simDCache(0x364, 1, &csim_result); // PC Relative Load ...@@ -94,6 +96,7 @@ memAccessCycles += simDCache(0x364, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x224, 40, &csim_result); memAccessCycles += simICache(0x224, 40, &csim_result);
estimate_power("mainbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 7 : 0); pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 7 : 0);
end_43 = 0; end_43 = 0;
count = 0; count = 0;
...@@ -114,6 +117,7 @@ mainbb_4: ...@@ -114,6 +117,7 @@ mainbb_4:
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
// Simulating I Cache for obj block 3 // Simulating I Cache for obj block 3
memAccessCycles += simICache(0x258, 20, &csim_result); memAccessCycles += simICache(0x258, 20, &csim_result);
estimate_power("mainbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0); pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
i_45 = (int) end_43; i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45]; ivtmp_34 = (uintptr_t)&in_Data[i_45];
...@@ -126,6 +130,7 @@ mainbb_5: ...@@ -126,6 +130,7 @@ mainbb_5:
memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0, &csim_result); memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0, &csim_result);
// Simulating I Cache for obj block 4 // Simulating I Cache for obj block 4
memAccessCycles += simICache(0x26c, 36, &csim_result); memAccessCycles += simICache(0x26c, 36, &csim_result);
estimate_power("mainbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179 // TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0); pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34); pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
...@@ -144,6 +149,7 @@ mainbb_6: ...@@ -144,6 +149,7 @@ mainbb_6:
// # PRED: 5 [1.0%] (false,exec) 3 [1.0%] (false,exec) // # PRED: 5 [1.0%] (false,exec) 3 [1.0%] (false,exec)
// Simulating I Cache for obj block 5 // Simulating I Cache for obj block 5
memAccessCycles += simICache(0x290, 40, &csim_result); memAccessCycles += simICache(0x290, 40, &csim_result);
estimate_power("mainbb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 7 : 0); pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr); adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr);
count = count + 1; count = count + 1;
...@@ -157,6 +163,7 @@ mainbb_13: ...@@ -157,6 +163,7 @@ mainbb_13:
// # PRED: 6 [91.0%] (true,exec) // # PRED: 6 [91.0%] (true,exec)
// Simulating I Cache for obj block 2 // Simulating I Cache for obj block 2
memAccessCycles += simICache(0x24c, 12, &csim_result); memAccessCycles += simICache(0x24c, 12, &csim_result);
estimate_power("mainbb_13", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
end_43 = end_46; end_43 = end_46;
goto mainbb_3; goto mainbb_3;
// # SUCC: 3 [100.0%] (fallthru) // # SUCC: 3 [100.0%] (fallthru)
...@@ -167,6 +174,7 @@ memAccessCycles += simDCache(0x358, 1, &csim_result); // PC Relative Load ...@@ -167,6 +174,7 @@ memAccessCycles += simDCache(0x358, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1, &csim_result); memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1, &csim_result);
// Simulating I Cache for obj block 6 // Simulating I Cache for obj block 6
memAccessCycles += simICache(0x2b8, 32, &csim_result); memAccessCycles += simICache(0x2b8, 32, &csim_result);
estimate_power("mainbb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 7 : 0); pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 7 : 0);
if (ARR_SIZE_0 % 10240 != 0) if (ARR_SIZE_0 % 10240 != 0)
goto mainbb_8; goto mainbb_8;
...@@ -179,6 +187,7 @@ mainbb_8: ...@@ -179,6 +187,7 @@ mainbb_8:
memAccessCycles += simDCache(0x354, 1, &csim_result); // PC Relative Load memAccessCycles += simDCache(0x354, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 7 // Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2d8, 24, &csim_result); memAccessCycles += simICache(0x2d8, 24, &csim_result);
estimate_power("mainbb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 7 : 0); pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
start_40 = j * 10240; start_40 = j * 10240;
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result); memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
...@@ -195,6 +204,7 @@ memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load ...@@ -195,6 +204,7 @@ memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 8 // Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2f0, 28, &csim_result); memAccessCycles += simICache(0x2f0, 28, &csim_result);
estimate_power("mainbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0); pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
i = (int) start_40; i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i]; ivtmp_28 = (uintptr_t)&in_Data[i];
...@@ -208,6 +218,7 @@ mainbb_10: ...@@ -208,6 +218,7 @@ mainbb_10:
memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0, &csim_result); memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0, &csim_result);
// Simulating I Cache for obj block 9 // Simulating I Cache for obj block 9
memAccessCycles += simICache(0x30c, 36, &csim_result); memAccessCycles += simICache(0x30c, 36, &csim_result);
estimate_power("mainbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Inaccurately Matched Load at line 219 // TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0); pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result); memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result);
...@@ -229,6 +240,7 @@ memAccessCycles += simDCache(0x364, 1, &csim_result); // PC Relative Load ...@@ -229,6 +240,7 @@ memAccessCycles += simDCache(0x364, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 10 // Simulating I Cache for obj block 10
memAccessCycles += simICache(0x330, 20, &csim_result); memAccessCycles += simICache(0x330, 20, &csim_result);
estimate_power("mainbb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 7 : 0); pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr); adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr);
// # SUCC: 12 [100.0%] (fallthru,exec) // # SUCC: 12 [100.0%] (fallthru,exec)
...@@ -237,9 +249,11 @@ mainbb_12: ...@@ -237,9 +249,11 @@ mainbb_12:
// # PRED: 7 [39.0%] (false,exec) 11 [100.0%] (fallthru,exec) // # PRED: 7 [39.0%] (false,exec) 11 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 11 // Simulating I Cache for obj block 11
memAccessCycles += simICache(0x344, 16, &csim_result); memAccessCycles += simICache(0x344, 16, &csim_result);
estimate_power("mainbb_12", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
printf("memAccessCycles = \%llu\n", memAccessCycles); printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles); printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini(&csim_result); cacheSimFini(&csim_result);
power_estimator_fini();
pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 7 : 0); pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 7 : 0);
return 0; return 0;
// # SUCC: EXIT [100.0%] // # SUCC: EXIT [100.0%]
......
instrument/examples/adpcm/instrumented/power_trace.dat 0 → 100644
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instrument/examples/adpcm/instrumented/power_trace_10000.dat 0 → 100644
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instrument/examples/adpcm/instrumented/power_trace_100000.dat 0 → 100644
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instrument/examples/adpcm/instrumented_manual_new/Makefile 0 → 100644
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include ../../../../cache_simulator/Makefile.macros
include ../../../../branch_predictor/Makefile.macros
CC = gcc
CFLAGS = -O2 -std=c99
INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS)
LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB)
APP_SOURCES = my_ctop_IR.c adpcm_IR.c
all: my_ctop_IR.out
my_ctop_IR.out: $(APP_SOURCES)
$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred
check: my_ctop_IR.out
export LD_LIBRARY_PATH=$(CACHESIM_LIB)
./my_ctop_IR.out
clean:
rm -rf *.o my_ctop_IR.out
instrument/examples/adpcm/instrumented_manual_new/adpcm.h 0 → 100644
View file @ 4c4e8d5e
/*
** adpcm.h - include file for adpcm coder.
**
** Version 1.0, 7-Jul-92.
*/
struct adpcm_state {
short valprev; /* Previous output value */
char index; /* Index into stepsize table */
};
#ifdef __STDC__
#define ARGS(x) x
#else
#define ARGS(x) ()
#endif
void adpcm_coder (short indata[], unsigned long indata_addr, char outdata[], unsigned long outdata_addr, int len, struct adpcm_state *state, unsigned long state_addr);
instrument/examples/adpcm/instrumented_manual_new/adpcm_IR.c 0 → 100644
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instrument/examples/adpcm/instrumented_manual_new/in_small.h 0 → 100644
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instrument/examples/adpcm/instrumented_manual_new/my_ctop_IR.c 0 → 100644
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/***********************************************************
Intermediate representation of
adpcm/app_dir/my_ctop.c
Converted by ir2c v0.1
***********************************************************/
#include <limits.h>
#include <stdint.h>
#include "ir2c.h"
#include "cacheSim.h"
#include "branchPred.h"
unsigned long SP = 0x1fffb8;
unsigned long long memAccessCycles = 0;
unsigned long long pipelineCycles = 0;
struct csim_result_t csim_result;
/*
** Timing - Test timing on adpcm coder and decoder.
**
** The program creates 10Kb garbage, and runs the compressor and
** the decompressor on it.
*/
/*sds*/
#include <stdio.h>
#include "adpcm.h"
#include "in_small.h"
//#include "in_large.h"
#include "my_variables.h"
#define DATASIZE 10*1024 /* Data block size */
//ARR_SIZE is the number of short type elements in
//input data array. defined in in_data_small.h
//unsigned int ARR_SIZE = 13305601;
//unsigned int ARR_SIZE = 684433;
short int pcmdata[DATASIZE];
unsigned long pcmdata_addr = 0x14f208;
char adpcmdata[DATASIZE/2];
unsigned long adpcmdata_addr = 0x154208;
int a[123];
struct adpcm_state coder_1_state;
unsigned long coder_1_state_addr = 0x14f204;
int main() {
long unsigned int end_46;
int i_45;
long unsigned int end_44;
long unsigned int end_43;
long unsigned int start_40;
uintptr_t ivtmp_34;
int D_2229;
uintptr_t ivtmp_28;
long unsigned int count;
long unsigned int end;
long unsigned int start;
long unsigned int j;
int i;
unsigned int ARR_SIZE_0;
unsigned long ARR_SIZE_0_addr = 0x0;
unsigned long ivtmp_34_addr = 0; // MANUAL
unsigned long ivtmp_28_addr = 0;
mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(&csim_result);
branchPred_init();
SP = SP + 0x30;
memAccessCycles += simDCache(0x354, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x358, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0, &csim_result);
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 36, &csim_result);
pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 7 : 0);
ARR_SIZE_0 = ARR_SIZE;
j = ARR_SIZE_0 / 10240;
if (j != 0)
goto mainbb_14;
else
goto mainbb_7;
// # SUCC: 14 [91.0%] (true,exec) 7 [9.0%] (false,exec)
mainbb_14:
// # PRED: 2 [91.0%] (true,exec)
memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Spilling Register
memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x364, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x224, 40, &csim_result);
pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 7 : 0);
end_43 = 0;
count = 0;
// # SUCC: 3 [100.0%] (fallthru)
mainbb_3:
// # PRED: 13 [100.0%] (fallthru) 14 [100.0%] (fallthru)
pipelineCycles += 9 - (enterBlock(0xa9, 0xab) ? 7 : 0);
end_46 = end_43 + 10240;
if (end_43 < end_46)
goto mainbb_4;
else
goto mainbb_6;
// # SUCC: 4 [99.0%] (true,exec) 6 [1.0%] (false,exec)
mainbb_4:
// # PRED: 3 [99.0%] (true,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x258, 20, &csim_result);
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45];
ivtmp_34_addr = in_Data_addr + (2 * i_45);
end_44 = end_43;
// # SUCC: 5 [100.0%] (fallthru,exec)
mainbb_5:
// # PRED: 5 [99.0%] (true,exec) 4 [100.0%] (fallthru,exec)
memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0, &csim_result);
// Simulating I Cache for obj block 4
memAccessCycles += simICache(0x26c, 36, &csim_result);
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
memAccessCycles += simDCache(ivtmp_34_addr, 1, &csim_result);
i_45 = i_45 + 1;
end_44 = (long unsigned int) i_45;
ivtmp_34 = ivtmp_34 + 2;
ivtmp_34_addr = ivtmp_34_addr + 2;
if (end_44 < end_46)
goto mainbb_5;
else
goto mainbb_6;
// # SUCC: 5 [99.0%] (true,exec) 6 [1.0%] (false,exec)
mainbb_6:
// # PRED: 5 [1.0%] (false,exec) 3 [1.0%] (false,exec)
// Simulating I Cache for obj block 5
memAccessCycles += simICache(0x290, 40, &csim_result);
pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr);
count = count + 1;
if (j > count)
goto mainbb_13;
else
goto mainbb_7;
// # SUCC: 13 [91.0%] (true,exec) 7 [9.0%] (false,exec)
mainbb_13:
// # PRED: 6 [91.0%] (true,exec)
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x24c, 12, &csim_result);
end_43 = end_46;
goto mainbb_3;
// # SUCC: 3 [100.0%] (fallthru)
mainbb_7:
// # PRED: 6 [9.0%] (false,exec) 2 [9.0%] (false,exec)
memAccessCycles += simDCache(0x358, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1, &csim_result);
// Simulating I Cache for obj block 6
memAccessCycles += simICache(0x2b8, 32, &csim_result);
pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 7 : 0);
if (ARR_SIZE_0 % 10240 != 0)
goto mainbb_8;
else
goto mainbb_12;
// # SUCC: 8 [61.0%] (true,exec) 12 [39.0%] (false,exec)
mainbb_8:
// # PRED: 7 [61.0%] (true,exec)
memAccessCycles += simDCache(0x354, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2d8, 24, &csim_result);
pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
start_40 = j * 10240;
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
end = ARR_SIZE;
if (start_40 < end)
goto mainbb_9;
else
goto mainbb_11;
// # SUCC: 9 [99.0%] (true,exec) 11 [1.0%] (false,exec)
mainbb_9:
// # PRED: 8 [99.0%] (true,exec)
memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2f0, 28, &csim_result);
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i];
ivtmp_28_addr = in_Data_addr + (2 * i);
D_2229 = (int) end;
start = start_40;
// # SUCC: 10 [100.0%] (fallthru,exec)
mainbb_10:
// # PRED: 10 [99.0%] (true,exec) 9 [100.0%] (fallthru,exec)
memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0, &csim_result);
// Simulating I Cache for obj block 9
memAccessCycles += simICache(0x30c, 36, &csim_result);
// TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result);
pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
i = i + 1;
start = (long unsigned int) i;
ivtmp_28 = ivtmp_28 + 2;
ivtmp_28_addr = ivtmp_28_addr + 2;
if (i != D_2229)
goto mainbb_10;
else
goto mainbb_11;
// # SUCC: 10 [99.0%] (true,exec) 11 [1.0%] (false,exec)
mainbb_11:
// # PRED: 10 [1.0%] (false,exec) 8 [1.0%] (false,exec)
memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x364, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 10
memAccessCycles += simICache(0x330, 20, &csim_result);
pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr);
// # SUCC: 12 [100.0%] (fallthru,exec)
mainbb_12:
// # PRED: 7 [39.0%] (false,exec) 11 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 11
memAccessCycles += simICache(0x344, 16, &csim_result);
printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini(&csim_result);
pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 7 : 0);
return 0;
// # SUCC: EXIT [100.0%]
}
instrument/examples/adpcm/instrumented_manual_new/my_variables.h 0 → 100644
View file @ 4c4e8d5e
// unsigned int ARR_SIZE = 13305601;
unsigned int ARR_SIZE = 684433;
unsigned long ARR_SIZE_addr = 0xaa0;
instrument/examples/sieve/instrumented/Makefile
View file @ 4c4e8d5e
include ../../../../cache_simulator/Makefile.macros include ../../../../cache_simulator/Makefile.macros
include ../../../../branch_predictor/Makefile.macros include ../../../../branch_predictor/Makefile.macros
include ../../../../power_estimator/Makefile.macros
CC = gcc CC = gcc
CFLAGS = -O2 -std=c99 CFLAGS = -O2 -std=c99
INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS) INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS) -I$(POWEREST_HEADERS)
LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB) LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB) -L$(POWEREST_LIB)
APP_SOURCES = erat_sieve_no_print_IR.c APP_SOURCES = erat_sieve_no_print_IR.c
all: sieve.out all: sieve.out
sieve.out: $(APP_SOURCES) sieve.out: $(APP_SOURCES)
$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred $(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred -lpowerEst
clean: clean:
rm -rf *.o cacheSimTest rm -rf *.o cacheSimTest
......
instrument/examples/sieve/instrumented/erat_sieve_no_print_IR.c
View file @ 4c4e8d5e
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#include "ir2c.h" #include "ir2c.h"
#include "cacheSim.h" #include "cacheSim.h"
#include "branchPred.h" #include "branchPred.h"
#include "power_estimator.h"
unsigned long SP = 0x1234; unsigned long SP = 0x1234;
unsigned long long memAccessCycles = 0; unsigned long long memAccessCycles = 0;
unsigned long long pipelineCycles = 0; unsigned long long pipelineCycles = 0;
...@@ -40,7 +41,7 @@ void sieve_func() { ...@@ -40,7 +41,7 @@ void sieve_func() {
uintptr_t D_2240; uintptr_t D_2240;
uintptr_t D_2230; uintptr_t D_2230;
uintptr_t ivtmp_36; uintptr_t ivtmp_36;
unsigned long ivtmp_36_addr; //MANUAL unsigned long ivtmp_36_addr; // MANUAL
int j; int j;
int i; int i;
unsigned int sieve[500000]; unsigned int sieve[500000];
...@@ -52,6 +53,7 @@ SP = SP + 0x1e84a0; ...@@ -52,6 +53,7 @@ SP = SP + 0x1e84a0;
memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 40, &csim_result); memAccessCycles += simICache(0x200, 40, &csim_result);
estimate_power("sieve_funcbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 24 - (enterBlock(0x96, 0x9f) ? 7 : 0); pipelineCycles += 24 - (enterBlock(0x96, 0x9f) ? 7 : 0);
ivtmp_68 = 0; ivtmp_68 = 0;
// # SUCC: 3 [100.0%] (fallthru,exec) // # SUCC: 3 [100.0%] (fallthru,exec)
...@@ -61,6 +63,7 @@ sieve_funcbb_3: ...@@ -61,6 +63,7 @@ sieve_funcbb_3:
memAccessCycles += simDCache(results_addr + (+ivtmp_68), 0, &csim_result); memAccessCycles += simDCache(results_addr + (+ivtmp_68), 0, &csim_result);
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x228, 28, &csim_result); memAccessCycles += simICache(0x228, 28, &csim_result);
estimate_power("sieve_funcbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xa0, 0xa6) ? 7 : 0); pipelineCycles += 13 - (enterBlock(0xa0, 0xa6) ? 7 : 0);
*(unsigned int*)((uintptr_t)&results + (uintptr_t)ivtmp_68) = 0; *(unsigned int*)((uintptr_t)&results + (uintptr_t)ivtmp_68) = 0;
memAccessCycles += simDCache((SP + sieve_addr + (+ivtmp_68)), 0, &csim_result); memAccessCycles += simDCache((SP + sieve_addr + (+ivtmp_68)), 0, &csim_result);
...@@ -76,6 +79,7 @@ sieve_funcbb_17: ...@@ -76,6 +79,7 @@ sieve_funcbb_17:
// # PRED: 3 [1.0%] (false,exec) // # PRED: 3 [1.0%] (false,exec)
// Simulating I Cache for obj block 2 // Simulating I Cache for obj block 2
memAccessCycles += simICache(0x244, 52, &csim_result); memAccessCycles += simICache(0x244, 52, &csim_result);
estimate_power("sieve_funcbb_17", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 21 - (enterBlock(0xa7, 0xb3) ? 7 : 0); pipelineCycles += 21 - (enterBlock(0xa7, 0xb3) ? 7 : 0);
ivtmp_49 = 6; ivtmp_49 = 6;
ivtmp_58 = 4; ivtmp_58 = 4;
...@@ -86,6 +90,7 @@ sieve_funcbb_4: ...@@ -86,6 +90,7 @@ sieve_funcbb_4:
// # PRED: 7 [99.0%] (true,exec) 17 [100.0%] (fallthru) // # PRED: 7 [99.0%] (true,exec) 17 [100.0%] (fallthru)
// Simulating I Cache for obj block 3 // Simulating I Cache for obj block 3
memAccessCycles += simICache(0x278, 16, &csim_result); memAccessCycles += simICache(0x278, 16, &csim_result);
estimate_power("sieve_funcbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0xb4, 0xb7) ? 7 : 0); pipelineCycles += 9 - (enterBlock(0xb4, 0xb7) ? 7 : 0);
D_2263 = (unsigned int) i_72; D_2263 = (unsigned int) i_72;
memAccessCycles += simDCache((SP + sieve_addr + (+D_2263*4)), 1, &csim_result); memAccessCycles += simDCache((SP + sieve_addr + (+D_2263*4)), 1, &csim_result);
...@@ -99,6 +104,7 @@ sieve_funcbb_5: ...@@ -99,6 +104,7 @@ sieve_funcbb_5:
// # PRED: 4 [50.0%] (true,exec) // # PRED: 4 [50.0%] (true,exec)
// Simulating I Cache for obj block 4 // Simulating I Cache for obj block 4
memAccessCycles += simICache(0x288, 12, &csim_result); memAccessCycles += simICache(0x288, 12, &csim_result);
estimate_power("sieve_funcbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 8 - (enterBlock(0xb8, 0xba) ? 7 : 0); pipelineCycles += 8 - (enterBlock(0xb8, 0xba) ? 7 : 0);
j_76 = (int) ivtmp_58; j_76 = (int) ivtmp_58;
if (j_76 <= 499999) if (j_76 <= 499999)
...@@ -111,6 +117,7 @@ sieve_funcbb_18: ...@@ -111,6 +117,7 @@ sieve_funcbb_18:
// # PRED: 5 [91.0%] (true,exec) // # PRED: 5 [91.0%] (true,exec)
// Simulating I Cache for obj block 5 // Simulating I Cache for obj block 5
memAccessCycles += simICache(0x294, 4, &csim_result); memAccessCycles += simICache(0x294, 4, &csim_result);
estimate_power("sieve_funcbb_18", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 8 - (enterBlock(0xbb, 0xbb) ? 7 : 0); pipelineCycles += 8 - (enterBlock(0xbb, 0xbb) ? 7 : 0);
ivtmp_74 = ivtmp_49; ivtmp_74 = ivtmp_49;
// # SUCC: 6 [100.0%] (fallthru) // # SUCC: 6 [100.0%] (fallthru)
...@@ -120,6 +127,7 @@ sieve_funcbb_6: ...@@ -120,6 +127,7 @@ sieve_funcbb_6:
memAccessCycles += simDCache((SP + sieve_addr + (4 * (j_76))), 0, &csim_result); memAccessCycles += simDCache((SP + sieve_addr + (4 * (j_76))), 0, &csim_result);
// Simulating I Cache for obj block 6 // Simulating I Cache for obj block 6
memAccessCycles += simICache(0x298, 40, &csim_result); memAccessCycles += simICache(0x298, 40, &csim_result);
estimate_power("sieve_funcbb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 17 - (enterBlock(0xbc, 0xc5) ? 7 : 0); pipelineCycles += 17 - (enterBlock(0xbc, 0xc5) ? 7 : 0);
sieve[j_76] = 0; sieve[j_76] = 0;
D_2252 = (unsigned int) j_76 + D_2263; D_2252 = (unsigned int) j_76 + D_2263;
...@@ -135,6 +143,7 @@ sieve_funcbb_7: ...@@ -135,6 +143,7 @@ sieve_funcbb_7:
// # PRED: 4 [50.0%] (false,exec) 6 [9.0%] (false,exec) 5 [9.0%] (false,exec) // # PRED: 4 [50.0%] (false,exec) 6 [9.0%] (false,exec) 5 [9.0%] (false,exec)
// Simulating I Cache for obj block 7 // Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2c0, 24, &csim_result); memAccessCycles += simICache(0x2c0, 24, &csim_result);
estimate_power("sieve_funcbb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0xc6, 0xcb) ? 7 : 0); pipelineCycles += 19 - (enterBlock(0xc6, 0xcb) ? 7 : 0);
i_72 = i_72 + 1; i_72 = i_72 + 1;
ivtmp_58 = ivtmp_58 + 2; ivtmp_58 = ivtmp_58 + 2;
...@@ -150,6 +159,7 @@ sieve_funcbb_8: ...@@ -150,6 +159,7 @@ sieve_funcbb_8:
memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 8 // Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2d8, 24, &csim_result); memAccessCycles += simICache(0x2d8, 24, &csim_result);
estimate_power("sieve_funcbb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xcc, 0xd1) ? 7 : 0); pipelineCycles += 13 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
j = 2; j = 2;
i = 0; i = 0;
...@@ -177,6 +187,7 @@ sieve_funcbb_11: ...@@ -177,6 +187,7 @@ sieve_funcbb_11:
// # PRED: 9 [50.0%] (false,exec) 10 [100.0%] (fallthru,exec) // # PRED: 9 [50.0%] (false,exec) 10 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 9 // Simulating I Cache for obj block 9
memAccessCycles += simICache(0x2f0, 28, &csim_result); memAccessCycles += simICache(0x2f0, 28, &csim_result);
estimate_power("sieve_funcbb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
j = j + 1; j = j + 1;
if (j != 500000) if (j != 500000)
goto sieve_funcbb_9; goto sieve_funcbb_9;
...@@ -190,6 +201,7 @@ memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load ...@@ -190,6 +201,7 @@ memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(results_addr + (4 * (0)), 1, &csim_result); memAccessCycles += simDCache(results_addr + (4 * (0)), 1, &csim_result);
// Simulating I Cache for obj block 10 // Simulating I Cache for obj block 10
memAccessCycles += simICache(0x30c, 16, &csim_result); memAccessCycles += simICache(0x30c, 16, &csim_result);
estimate_power("sieve_funcbb_12", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0xd9, 0xdc) ? 7 : 0); pipelineCycles += 9 - (enterBlock(0xd9, 0xdc) ? 7 : 0);
if (results[0] == 0) if (results[0] == 0)
goto sieve_funcbb_16; goto sieve_funcbb_16;
...@@ -201,6 +213,7 @@ sieve_funcbb_13: ...@@ -201,6 +213,7 @@ sieve_funcbb_13:
// # PRED: 12 [95.5%] (false,exec) // # PRED: 12 [95.5%] (false,exec)
// Simulating I Cache for obj block 11 // Simulating I Cache for obj block 11
memAccessCycles += simICache(0x31c, 12, &csim_result); memAccessCycles += simICache(0x31c, 12, &csim_result);
estimate_power("sieve_funcbb_13", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 10 - (enterBlock(0xdd, 0xdf) ? 7 : 0); pipelineCycles += 10 - (enterBlock(0xdd, 0xdf) ? 7 : 0);
ivtmp_36 = (uintptr_t)&results; ivtmp_36 = (uintptr_t)&results;
ivtmp_36_addr = results_addr; ivtmp_36_addr = results_addr;
...@@ -211,6 +224,7 @@ sieve_funcbb_14: ...@@ -211,6 +224,7 @@ sieve_funcbb_14:
// # PRED: 15 [98.9%] (true,exec) 13 [100.0%] (fallthru,exec) // # PRED: 15 [98.9%] (true,exec) 13 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 12 // Simulating I Cache for obj block 12
memAccessCycles += simICache(0x328, 12, &csim_result); memAccessCycles += simICache(0x328, 12, &csim_result);
estimate_power("sieve_funcbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar results at line 224 // TODO: UnmappedLS: Load GlobalVar results at line 224
pipelineCycles += 8 - (enterBlock(0xe0, 0xe2) ? 7 : 0); pipelineCycles += 8 - (enterBlock(0xe0, 0xe2) ? 7 : 0);
memAccessCycles += simDCache(ivtmp_36_addr + 4, 1, &csim_result); memAccessCycles += simDCache(ivtmp_36_addr + 4, 1, &csim_result);
...@@ -224,6 +238,7 @@ sieve_funcbb_15: ...@@ -224,6 +238,7 @@ sieve_funcbb_15:
// # PRED: 14 [95.5%] (false,exec) // # PRED: 14 [95.5%] (false,exec)
// Simulating I Cache for obj block 13 // Simulating I Cache for obj block 13
memAccessCycles += simICache(0x334, 12, &csim_result); memAccessCycles += simICache(0x334, 12, &csim_result);
estimate_power("sieve_funcbb_15", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0xe3, 0xe5) ? 7 : 0); pipelineCycles += 9 - (enterBlock(0xe3, 0xe5) ? 7 : 0);
ivtmp_36 = ivtmp_36 + 4; ivtmp_36 = ivtmp_36 + 4;
ivtmp_36_addr = ivtmp_36_addr + 4; ivtmp_36_addr = ivtmp_36_addr + 4;
...@@ -239,6 +254,7 @@ memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load ...@@ -239,6 +254,7 @@ memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(m_addr, 0, &csim_result); memAccessCycles += simDCache(m_addr, 0, &csim_result);
// Simulating I Cache for obj block 14 // Simulating I Cache for obj block 14
memAccessCycles += simICache(0x340, 28, &csim_result); memAccessCycles += simICache(0x340, 28, &csim_result);
estimate_power("sieve_funcbb_16", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 20 - (enterBlock(0xe6, 0xec) ? 7 : 0); pipelineCycles += 20 - (enterBlock(0xe6, 0xec) ? 7 : 0);
m.v = 0; m.v = 0;
return; return;
...@@ -253,14 +269,17 @@ mainbb_2: ...@@ -253,14 +269,17 @@ mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec) // # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(&csim_result); cacheSimInit(&csim_result);
branchPred_init(); branchPred_init();
power_estimator_init();
SP = SP + 0x8; SP = SP + 0x8;
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x364, 20, &csim_result); memAccessCycles += simICache(0x364, 20, &csim_result);
estimate_power("mainbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 12 - (enterBlock(0xf1, 0xf5) ? 7 : 0); pipelineCycles += 12 - (enterBlock(0xf1, 0xf5) ? 7 : 0);
sieve_func (); sieve_func ();
printf("memAccessCycles = \%llu\n", memAccessCycles); printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles); printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini(&csim_result); cacheSimFini(&csim_result);
power_estimator_fini();
return 0; return 0;
// # SUCC: EXIT [100.0%] // # SUCC: EXIT [100.0%]
......
instrument/examples/sieve/instrumented/power_trace.dat 0 → 100644
View file @ 4c4e8d5e
This diff is collapsed.
instrument/examples/sieve/instrumented/power_trace_100000.dat 0 → 100644
View file @ 4c4e8d5e
This diff is collapsed.
instrument/examples/sieve/instrumented_manual_new/Makefile 0 → 100644
View file @ 4c4e8d5e
include ../../../../cache_simulator/Makefile.macros
include ../../../../branch_predictor/Makefile.macros
CC = gcc
CFLAGS = -O2 -std=c99
INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS)
LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB)
APP_SOURCES = erat_sieve_no_print_IR.c
all: sieve.out
sieve.out: $(APP_SOURCES)
$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred
clean:
rm -rf *.o cacheSimTest
for f in $(SOURCES); do \
rm -rf $$f; \
done
instrument/examples/sieve/instrumented_manual_new/erat_sieve_no_print_IR.c 0 → 100644
View file @ 4c4e8d5e
/***********************************************************
Intermediate representation of
sieve/app_dir/erat_sieve_no_print.c
Converted by ir2c v0.1
***********************************************************/
#include <limits.h>
#include <stdint.h>
#include "ir2c.h"
#include "cacheSim.h"
#include "branchPred.h"
unsigned long SP = 0x1234;
unsigned long long memAccessCycles = 0;
unsigned long long pipelineCycles = 0;
struct csim_result_t csim_result;
#include <stdio.h>
#define N 500000
unsigned int results[N];
unsigned long results_addr = 0xc0c;
struct test {
unsigned int v;
unsigned int k;
} m = { 1, 1 };
unsigned long m_addr = 0x7c8;
void sieve_func() {
int j_76;
uintptr_t ivtmp_74;
int i_72;
uintptr_t ivtmp_68;
uintptr_t D_2263;
uintptr_t ivtmp_58;
uintptr_t D_2252;
uintptr_t ivtmp_49;
uintptr_t D_2240;
uintptr_t D_2230;
uintptr_t ivtmp_36;
unsigned long ivtmp_36_addr; //MANUAL
int j;
int i;
unsigned int sieve[500000];
unsigned long sieve_addr = 0x0;
sieve_funcbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
SP = SP + 0x1e84a0;
memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 40, &csim_result);
pipelineCycles += 24 - (enterBlock(0x96, 0x9f) ? 7 : 0);
ivtmp_68 = 0;
// # SUCC: 3 [100.0%] (fallthru,exec)
sieve_funcbb_3:
// # PRED: 3 [99.0%] (true,exec) 2 [100.0%] (fallthru,exec)
memAccessCycles += simDCache(results_addr + (+ivtmp_68), 0, &csim_result);
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x228, 28, &csim_result);
pipelineCycles += 13 - (enterBlock(0xa0, 0xa6) ? 7 : 0);
*(unsigned int*)((uintptr_t)&results + (uintptr_t)ivtmp_68) = 0;
memAccessCycles += simDCache((SP + sieve_addr + (+ivtmp_68)), 0, &csim_result);
*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)ivtmp_68) = 1;
ivtmp_68 = ivtmp_68 + 4;
if (ivtmp_68 != 2000000)
goto sieve_funcbb_3;
else
goto sieve_funcbb_17;
// # SUCC: 3 [99.0%] (true,exec) 17 [1.0%] (false,exec)
sieve_funcbb_17:
// # PRED: 3 [1.0%] (false,exec)
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x244, 52, &csim_result);
pipelineCycles += 21 - (enterBlock(0xa7, 0xb3) ? 7 : 0);
ivtmp_49 = 6;
ivtmp_58 = 4;
i_72 = 2;
// # SUCC: 4 [100.0%] (fallthru)
sieve_funcbb_4:
// # PRED: 7 [99.0%] (true,exec) 17 [100.0%] (fallthru)
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x278, 16, &csim_result);
pipelineCycles += 9 - (enterBlock(0xb4, 0xb7) ? 7 : 0);
D_2263 = (unsigned int) i_72;
memAccessCycles += simDCache((SP + sieve_addr + (+D_2263*4)), 1, &csim_result);
if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2263 * 4) != 0)
goto sieve_funcbb_5;
else
goto sieve_funcbb_7;
// # SUCC: 5 [50.0%] (true,exec) 7 [50.0%] (false,exec)
sieve_funcbb_5:
// # PRED: 4 [50.0%] (true,exec)
// Simulating I Cache for obj block 4
memAccessCycles += simICache(0x288, 12, &csim_result);
pipelineCycles += 8 - (enterBlock(0xb8, 0xba) ? 7 : 0);
j_76 = (int) ivtmp_58;
if (j_76 <= 499999)
goto sieve_funcbb_18;
else
goto sieve_funcbb_7;
// # SUCC: 18 [91.0%] (true,exec) 7 [9.0%] (false,exec)
sieve_funcbb_18:
// # PRED: 5 [91.0%] (true,exec)
// Simulating I Cache for obj block 5
memAccessCycles += simICache(0x294, 4, &csim_result);
pipelineCycles += 8 - (enterBlock(0xbb, 0xbb) ? 7 : 0);
ivtmp_74 = ivtmp_49;
// # SUCC: 6 [100.0%] (fallthru)
sieve_funcbb_6:
// # PRED: 6 [91.0%] (true,exec) 18 [100.0%] (fallthru)
memAccessCycles += simDCache((SP + sieve_addr + (4 * (j_76))), 0, &csim_result);
// Simulating I Cache for obj block 6
memAccessCycles += simICache(0x298, 40, &csim_result);
pipelineCycles += 17 - (enterBlock(0xbc, 0xc5) ? 7 : 0);
sieve[j_76] = 0;
D_2252 = (unsigned int) j_76 + D_2263;
j_76 = (int) D_2252;
ivtmp_74 = D_2263 + ivtmp_74;
if ((int) (ivtmp_74 - D_2263) <= 499999)
goto sieve_funcbb_6;
else
goto sieve_funcbb_7;
// # SUCC: 6 [91.0%] (true,exec) 7 [9.0%] (false,exec)
sieve_funcbb_7:
// # PRED: 4 [50.0%] (false,exec) 6 [9.0%] (false,exec) 5 [9.0%] (false,exec)
// Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2c0, 24, &csim_result);
pipelineCycles += 19 - (enterBlock(0xc6, 0xcb) ? 7 : 0);
i_72 = i_72 + 1;
ivtmp_58 = ivtmp_58 + 2;
ivtmp_49 = ivtmp_49 + 3;
if (i_72 * i_72 <= 499999)
goto sieve_funcbb_4;
else
goto sieve_funcbb_8;
// # SUCC: 4 [99.0%] (true,exec) 8 [1.0%] (false,exec)
sieve_funcbb_8:
// # PRED: 7 [1.0%] (false,exec)
memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2d8, 24, &csim_result);
pipelineCycles += 13 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
j = 2;
i = 0;
// # SUCC: 9 [100.0%] (fallthru,exec)
sieve_funcbb_9:
// # PRED: 11 [99.0%] (true,exec) 8 [100.0%] (fallthru,exec)
pipelineCycles += 12 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
D_2240 = (unsigned int) j;
memAccessCycles += simDCache((SP + sieve_addr + (+D_2240*4)), 1, &csim_result);
if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2240 * 4) != 0)
goto sieve_funcbb_10;
else
goto sieve_funcbb_11;
// # SUCC: 10 [50.0%] (true,exec) 11 [50.0%] (false,exec)
sieve_funcbb_10:
// # PRED: 9 [50.0%] (true,exec)
memAccessCycles += simDCache(results_addr + (4 * (i)), 0, &csim_result);
results[i] = D_2240;
i = i + 1;
// # SUCC: 11 [100.0%] (fallthru,exec)
sieve_funcbb_11:
// # PRED: 9 [50.0%] (false,exec) 10 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 9
memAccessCycles += simICache(0x2f0, 28, &csim_result);
j = j + 1;
if (j != 500000)
goto sieve_funcbb_9;
else
goto sieve_funcbb_12;
// # SUCC: 9 [99.0%] (true,exec) 12 [1.0%] (false,exec)
sieve_funcbb_12:
// # PRED: 11 [1.0%] (false,exec)
memAccessCycles += simDCache(0x35c, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(results_addr + (4 * (0)), 1, &csim_result);
// Simulating I Cache for obj block 10
memAccessCycles += simICache(0x30c, 16, &csim_result);
pipelineCycles += 9 - (enterBlock(0xd9, 0xdc) ? 7 : 0);
if (results[0] == 0)
goto sieve_funcbb_16;
else
goto sieve_funcbb_13;
// # SUCC: 16 [4.5%] (true,exec) 13 [95.5%] (false,exec)
sieve_funcbb_13:
// # PRED: 12 [95.5%] (false,exec)
// Simulating I Cache for obj block 11
memAccessCycles += simICache(0x31c, 12, &csim_result);
pipelineCycles += 10 - (enterBlock(0xdd, 0xdf) ? 7 : 0);
ivtmp_36 = (uintptr_t)&results;
ivtmp_36_addr = results_addr;
D_2230 = ivtmp_36 + 1999996;
// # SUCC: 14 [100.0%] (fallthru,exec)
sieve_funcbb_14:
// # PRED: 15 [98.9%] (true,exec) 13 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 12
memAccessCycles += simICache(0x328, 12, &csim_result);
// TODO: UnmappedLS: Load GlobalVar results at line 224
pipelineCycles += 8 - (enterBlock(0xe0, 0xe2) ? 7 : 0);
memAccessCycles += simDCache(ivtmp_36_addr + 4, 1, &csim_result);
if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0)
goto sieve_funcbb_16;
else
goto sieve_funcbb_15;
// # SUCC: 16 [4.5%] (true,exec) 15 [95.5%] (false,exec)
sieve_funcbb_15:
// # PRED: 14 [95.5%] (false,exec)
// Simulating I Cache for obj block 13
memAccessCycles += simICache(0x334, 12, &csim_result);
pipelineCycles += 9 - (enterBlock(0xe3, 0xe5) ? 7 : 0);
ivtmp_36 = ivtmp_36 + 4;
ivtmp_36_addr = ivtmp_36_addr + 4;
if (ivtmp_36 != D_2230)
goto sieve_funcbb_14;
else
goto sieve_funcbb_16;
// # SUCC: 14 [98.9%] (true,exec) 16 [1.1%] (false,exec)
sieve_funcbb_16:
// # PRED: 14 [4.5%] (true,exec) 15 [1.1%] (false,exec) 12 [4.5%] (true,exec)
memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load
memAccessCycles += simDCache(m_addr, 0, &csim_result);
// Simulating I Cache for obj block 14
memAccessCycles += simICache(0x340, 28, &csim_result);
pipelineCycles += 20 - (enterBlock(0xe6, 0xec) ? 7 : 0);
m.v = 0;
return;
// # SUCC: EXIT [100.0%]
}
int main (void) {
mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(&csim_result);
branchPred_init();
SP = SP + 0x8;
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x364, 20, &csim_result);
pipelineCycles += 12 - (enterBlock(0xf1, 0xf5) ? 7 : 0);
sieve_func ();
printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini(&csim_result);
return 0;
// # SUCC: EXIT [100.0%]
}
instrument/instrument.py
View file @ 4c4e8d5e
...@@ -61,6 +61,11 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables, ...@@ -61,6 +61,11 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables,
annot) annot)
annot_str = '#include "branchPred.h"' annot_str = '#include "branchPred.h"'
annot = Annotation(annot_str, ISCFileName, lineNum, False) annot = Annotation(annot_str, ISCFileName, lineNum, False)
addAnnotationToDict(dictAnnotVarFuncDecl,
lineNum,
annot)
annot_str = '#include "power_estimator.h"'
annot = Annotation(annot_str, ISCFileName, lineNum, False)
addAnnotationToDict(dictAnnotVarFuncDecl, addAnnotationToDict(dictAnnotVarFuncDecl,
lineNum, lineNum,
annot) annot)
...@@ -342,6 +347,9 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl ...@@ -342,6 +347,9 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl
annot_str = "branchPred_init();" annot_str = "branchPred_init();"
annot = Annotation(annot_str, funcISC.fileName, funcISC.cfg.listBlocks[0].startLine-1, False) annot = Annotation(annot_str, funcISC.fileName, funcISC.cfg.listBlocks[0].startLine-1, False)
addAnnotationToDict(dictAnnotLoadStore, funcISC.cfg.listBlocks[0].startLine-1, annot) addAnnotationToDict(dictAnnotLoadStore, funcISC.cfg.listBlocks[0].startLine-1, annot)
annot_str = "power_estimator_init();"
annot = Annotation(annot_str, funcISC.fileName, funcISC.cfg.listBlocks[0].startLine-1, False)
addAnnotationToDict(dictAnnotLoadStore, funcISC.cfg.listBlocks[0].startLine-1, annot)
funcObj = find(lambda fn: fn.functionName == funcISC.functionName, listObjdumpFunctions) funcObj = find(lambda fn: fn.functionName == funcISC.functionName, listObjdumpFunctions)
annot_str = "SP = SP + 0x%x;" % (funcObj.stackSize) annot_str = "SP = SP + 0x%x;" % (funcObj.stackSize)
...@@ -461,6 +469,11 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl ...@@ -461,6 +469,11 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl
annot) annot)
annot_str = "memAccessCycles += simICache(0x%x, %d, &csim_result);" % (blockStartAddress, blockSizeRounded) annot_str = "memAccessCycles += simICache(0x%x, %d, &csim_result);" % (blockStartAddress, blockSizeRounded)
annot = Annotation(annot_str, funcISC.fileName, blockISC.startLine-1, False) annot = Annotation(annot_str, funcISC.fileName, blockISC.startLine-1, False)
addAnnotationToDict(dictAnnotLoadStore,
blockISC.startLine-1,
annot)
annot_str = "estimate_power(\"%s\", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));" % (blockISC.name)
annot = Annotation(annot_str, funcISC.fileName, blockISC.startLine-1, False)
addAnnotationToDict(dictAnnotLoadStore, addAnnotationToDict(dictAnnotLoadStore,
blockISC.startLine-1, blockISC.startLine-1,
annot) annot)
...@@ -491,6 +504,9 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl ...@@ -491,6 +504,9 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl
annot_str = 'cacheSimFini(&csim_result);' annot_str = 'cacheSimFini(&csim_result);'
annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False) annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False)
addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot) addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot)
annot_str = 'power_estimator_fini();'
annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False)
addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot)
break break
else: else:
continue continue
......
power_estimator/headers/power_estimator.h
View file @ 4c4e8d5e
...@@ -7,7 +7,12 @@ ...@@ -7,7 +7,12 @@
* period of time, and generates the amount of energy used over the period. * period of time, and generates the amount of energy used over the period.
*/ */
extern double estimate_power(unsigned long long execCycles, extern double estimate_power(char *blockName,
unsigned long L1_Hits, unsigned long long execCycles,
unsigned long L2_Hits, unsigned long long memAccessCycles,
unsigned long L2_Misses); unsigned long long L2_Hits,
unsigned long long memAccesses);
extern void power_estimator_init();
extern void power_estimator_fini();
power_estimator/src/power_estimator.c
View file @ 4c4e8d5e
...@@ -32,11 +32,15 @@ double MEM_freq = 400; ...@@ -32,11 +32,15 @@ double MEM_freq = 400;
double MEM_volt = 1.2; double MEM_volt = 1.2;
double MEM_A_power; double MEM_A_power;
double MEM_C_power; double MEM_C_power;
unsigned int MEM_Access_Cycles = 50; unsigned int MEM_Access_Cycles = 200;
FILE *output_fp; FILE *output_fp;
unsigned long long totalCycles = 0; unsigned long long totalCycles = 0;
unsigned long long lastCyclePrinted = 0;
double lastEnergyPrinted = 0.0;
unsigned long long prev_execCycles = 0;
unsigned long long prev_memAccessCycles = 0;
unsigned long long prev_L2_Hits = 0; unsigned long long prev_L2_Hits = 0;
unsigned long long prev_memAccesses = 0; unsigned long long prev_memAccesses = 0;
...@@ -61,32 +65,51 @@ double estimate_power(char *blockName, ...@@ -61,32 +65,51 @@ double estimate_power(char *blockName,
unsigned long long startCycle; unsigned long long startCycle;
unsigned long long currBlock_L2_Hits; unsigned long long currBlock_L2_Hits;
unsigned long long currBlock_memAccesses; unsigned long long currBlock_memAccesses;
unsigned long long currBlock_execCycles;
unsigned long long currBlock_memAccessCycles;
double energy = 0.0; double energy = 0.0;
double power = 0.0; double power = 0.0;
startCycle = totalCycles; startCycle = totalCycles;
totalCycles += execCycles + memAccessCycles; totalCycles = execCycles + memAccessCycles;
currBlock_memAccessCycles = memAccessCycles - prev_memAccessCycles;
prev_memAccessCycles = memAccessCycles;
currBlock_execCycles = execCycles - prev_execCycles;
prev_execCycles = execCycles;
// CPU // CPU
energy = CPU_A_power * execCycles / CPU_freq; energy = CPU_A_power * currBlock_execCycles / CPU_freq;
energy += CPU_C_power * memAccessCycles / CPU_freq; energy += CPU_C_power * currBlock_memAccessCycles / CPU_freq;
// L2 // L2
currBlock_L2_Hits = prev_L2_Hits - L2_Hits; currBlock_L2_Hits = L2_Hits - prev_L2_Hits;
prev_L2_Hits = L2_Hits;
energy += L2_A_power * currBlock_L2_Hits * L2_Hit_Cycles / L2_freq; energy += L2_A_power * currBlock_L2_Hits * L2_Hit_Cycles / L2_freq;
energy += L2_C_power * (((totalCycles - startCycle) / CPU_freq) - (currBlock_L2_Hits * L2_Hit_Cycles / L2_freq)); energy += L2_C_power * (((totalCycles - startCycle) / CPU_freq) - (currBlock_L2_Hits * L2_Hit_Cycles / L2_freq));
// MEM // MEM
currBlock_memAccesses = prev_memAccesses - memAccesses; currBlock_memAccesses = memAccesses - prev_memAccesses;
prev_memAccesses = memAccesses;
energy += MEM_A_power * currBlock_memAccesses * MEM_Access_Cycles / MEM_freq; energy += MEM_A_power * currBlock_memAccesses * MEM_Access_Cycles / MEM_freq;
energy += MEM_C_power * (((totalCycles - startCycle) / CPU_freq) - (currBlock_memAccesses * MEM_Access_Cycles / MEM_freq)); energy += MEM_C_power * (((totalCycles - startCycle) / CPU_freq) - (currBlock_memAccesses * MEM_Access_Cycles / MEM_freq));
totalEnergy += energy; totalEnergy += energy;
power = energy / ((totalCycles - startCycle) / CPU_freq); // power = energy / ((totalCycles - startCycle) / CPU_freq);
if(startCycle - lastCyclePrinted > 10000)
{
power = (totalEnergy - lastEnergyPrinted) / ((startCycle - lastCyclePrinted) / CPU_freq);
lastCyclePrinted = startCycle;
lastEnergyPrinted = totalEnergy;
fprintf(output_fp, "%s, %llu, %f\n",
blockName, startCycle, power);
}
fprintf(output_fp, "%s, %llu, %f, %llu, %llu, %llu, %llu\n", // fprintf(output_fp, "%s, %llu, %f, %llu, %llu, %llu, %llu\n",
blockName, startCycle, power, execCycles, memAccessCycles, // blockName, startCycle, power, execCycles, memAccessCycles,
currBlock_L2_Hits, currBlock_memAccesses); // currBlock_L2_Hits, currBlock_memAccesses);
return power; return power;
} }
...@@ -95,14 +118,14 @@ void power_estimator_init() ...@@ -95,14 +118,14 @@ void power_estimator_init()
{ {
output_fp = fopen(POWER_OUTPUT_FILE, "w"); output_fp = fopen(POWER_OUTPUT_FILE, "w");
CPU_A_power = CPU_A_ABV * CPU_volt * CPU_volt * CPU_freq; CPU_A_power = CPU_A_ABV * CPU_volt * CPU_volt * CPU_freq / 1000.0;
CPU_C_power = CPU_C_ABV * CPU_volt * CPU_volt * CPU_freq; CPU_C_power = CPU_C_ABV * CPU_volt * CPU_volt * CPU_freq / 1000.0;
L2_A_power = L2_A_ABV * L2_volt * L2_volt * L2_freq; L2_A_power = L2_A_ABV * L2_volt * L2_volt * L2_freq / 1000.0;
L2_C_power = L2_C_ABV * L2_volt * L2_volt * L2_freq; L2_C_power = L2_C_ABV * L2_volt * L2_volt * L2_freq / 1000.0;
MEM_A_power = MEM_A_ABV * MEM_volt * MEM_volt * MEM_freq; MEM_A_power = MEM_A_ABV * MEM_volt * MEM_volt * MEM_freq / 1000.0;
MEM_C_power = MEM_C_ABV * MEM_volt * MEM_volt * MEM_freq; MEM_C_power = MEM_C_ABV * MEM_volt * MEM_volt * MEM_freq / 1000.0;
} }
void power_estimator_fini() void power_estimator_fini()
......
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