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hostCompiledSimulation
Commit 42c699db authored by Gaurav Kukreja's avatar Gaurav Kukreja
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adpcm instrumented changes 

Signed-off-by: Gaurav Kukreja's avatarGaurav Kukreja <gaurav@gauravk.in>
parent dbe4b755
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Showing with 17 additions and 17 deletions
instrument/examples/adpcm/instrumented_power/adpcm_IR.c
View file @ 42c699db
......@@ -125,7 +125,7 @@ memAccessCycles += simICache(0x36c, 44, &csim_result);
estimate_power("adpcm_coderbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 249
pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 5 : 0);
pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 7 : 0);
valpred = state->valprev;
memAccessCycles += simDCache(state_addr, 1, &csim_result);
index = state->index;
......@@ -145,7 +145,7 @@ memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x398, 32, &csim_result);
estimate_power("adpcm_coderbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 5 : 0);
pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
outp = outdata;
// memAccessCycles += simDCache(outdata_addr, 1, &csim_result);
ivtmp_28 = 0;
......@@ -155,7 +155,7 @@ pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 5 : 0);
adpcm_coderbb_4:
// # PRED: 18 [91.0%] (true,exec) 3 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
pipelineCycles += 58 - (enterBlock(0x106, 0x137) ? 5 : 0);
pipelineCycles += 68 - (enterBlock(0x106, 0x137) ? 7 : 0);
diff = (int) *(short int *)((uintptr_t)indata + (uintptr_t)ivtmp_28) - valpred;
memAccessCycles += simDCache(indata_addr + (+ivtmp_28), 1, &csim_result);
if (diff < 0)
......@@ -301,7 +301,7 @@ estimate_power("adpcm_coderbb_18", pipelineCycles, memAccessCycles, csim_result.
adpcm_coderbb_19:
// # PRED: 18 [9.0%] (false,exec)
pipelineCycles += 10 - (enterBlock(0x138, 0x13b) ? 5 : 0);
pipelineCycles += 10 - (enterBlock(0x138, 0x13b) ? 7 : 0);
if (bufferstep == 0)
goto adpcm_coderbb_20;
else
......@@ -328,7 +328,7 @@ memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Reg
memAccessCycles += simICache(0x490, 24, &csim_result);
// TODO: UnmappedLS: Store GlobalVar coder_1_state at line 317
// TODO: UnmappedLS: Store GlobalVar coder_1_state at line 318
pipelineCycles += 19 - (enterBlock(0x13c, 0x141) ? 5 : 0);
pipelineCycles += 19 - (enterBlock(0x13c, 0x141) ? 7 : 0);
state->valprev = (short int) (short int) valpred;
memAccessCycles += simDCache(state_addr, 0, &csim_result);
state->index = (char) (char) index;
......
instrument/examples/adpcm/instrumented_power/my_ctop_IR.c
View file @ 42c699db
......@@ -78,7 +78,7 @@ memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0, &csim_result);
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 36, &csim_result);
estimate_power("mainbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 5 : 0);
pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 7 : 0);
ARR_SIZE_0 = ARR_SIZE;
j = ARR_SIZE_0 / 10240;
if (j != 0)
......@@ -97,14 +97,14 @@ memAccessCycles += simICache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x224, 40, &csim_result);
estimate_power("mainbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 5 : 0);
pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 7 : 0);
end_43 = 0;
count = 0;
// # SUCC: 3 [100.0%] (fallthru)
mainbb_3:
// # PRED: 13 [100.0%] (fallthru) 14 [100.0%] (fallthru)
pipelineCycles += 9 - (enterBlock(0xa9, 0xab) ? 5 : 0);
pipelineCycles += 9 - (enterBlock(0xa9, 0xab) ? 7 : 0);
end_46 = end_43 + 10240;
if (end_43 < end_46)
goto mainbb_4;
......@@ -118,7 +118,7 @@ memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Reg
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x258, 20, &csim_result);
estimate_power("mainbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 5 : 0);
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45];
ivtmp_34_addr = in_Data_addr + (2 * i_45);
......@@ -132,7 +132,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0, &csim_resu
memAccessCycles += simICache(0x26c, 36, &csim_result);
estimate_power("mainbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 5 : 0);
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
memAccessCycles += simDCache(ivtmp_34_addr, 1, &csim_result);
i_45 = i_45 + 1;
......@@ -150,7 +150,7 @@ mainbb_6:
// Simulating I Cache for obj block 5
memAccessCycles += simICache(0x290, 40, &csim_result);
estimate_power("mainbb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 5 : 0);
pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr);
count = count + 1;
if (j > count)
......@@ -175,7 +175,7 @@ memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1, &csim_result);
// Simulating I Cache for obj block 6
memAccessCycles += simICache(0x2b8, 32, &csim_result);
estimate_power("mainbb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 5 : 0);
pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 7 : 0);
if (ARR_SIZE_0 % 10240 != 0)
goto mainbb_8;
else
......@@ -188,7 +188,7 @@ memAccessCycles += simICache(0x354, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2d8, 24, &csim_result);
estimate_power("mainbb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 5 : 0);
pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
start_40 = j * 10240;
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
end = ARR_SIZE;
......@@ -205,7 +205,7 @@ memAccessCycles += simICache(0x360, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2f0, 28, &csim_result);
estimate_power("mainbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 5 : 0);
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i];
ivtmp_28_addr = in_Data_addr + (2 * i);
......@@ -220,7 +220,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0, &csim_res
memAccessCycles += simICache(0x30c, 36, &csim_result);
estimate_power("mainbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 5 : 0);
pipelineCycles += 18 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result);
pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
i = i + 1;
......@@ -241,7 +241,7 @@ memAccessCycles += simICache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 10
memAccessCycles += simICache(0x330, 20, &csim_result);
estimate_power("mainbb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 5 : 0);
pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr);
// # SUCC: 12 [100.0%] (fallthru,exec)
......@@ -255,7 +255,7 @@ printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini(&csim_result);
power_estimator_fini();
branchPred_fini();
pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 5 : 0);
pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 7 : 0);
return 0;
// # SUCC: EXIT [100.0%]
......
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