Intermediate commit, very unstable.

Signed-off-by: Gaurav Kukreja <gaurav@gauravk.in>

cache_simulator/src/cortexA5HwMod.c

@@ -396,19 +396,27 @@ unsigned long long cortexA5_simICache(unsigned long address,
 	return latency;
 }
 
-
 unsigned long long cortexA5_simDCache(unsigned long address,
 		unsigned int isReadAccess,
 		struct csim_result_t *result)
 {
-	unsigned long long latency = 0;
+	unsigned int latency = 0;
 	unsigned long tag;
 	unsigned long index;
 	int setIndex = 0;
 	int replaceIndex;
 	int i;
 
-	// Lookup in L1
+	if (isReadAccess == 0 && L1DCacheConf.isWriteThrough == 1) // Write Access
+	{
+		// Simply increment latency by time to write to memory
+		latency += memWriteLatency;
+		L1D_Hit_Writethrough++;
+		return latency;
+	}
+	// For writeback, there is no latency. We can safely take this assumption,
+	//   as we are only using a Single Core System.
+
 	tag = getTagFromAddress(address, L1DCacheConf.tagLenBits, L1DCacheConf.tagMask);
 	index = getIndexFromAddress(address, L1DCacheConf.subIndexLenBits, L1DCacheConf.indexMask);
 
@@ -419,17 +427,11 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 		{
 			if (L1DCache[setIndex][index].tag == tag)
 			{
-				result->cyclesConsumed += L1DCacheConf.hitLatency;
 				latency += L1DCacheConf.hitLatency;
 				if (isReadAccess)
-				{
 					L1D_Hit_Read++;
-					result->L1Hits++;
-				}
-				else // Write Access
-				{
+				else
 					L1D_Hit_Writeback++;
-				}
 				return latency;
 			}
 		}
@@ -438,34 +440,16 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 			replaceIndex = setIndex;
 		}
 	}
-
-	// If here, data was not found in L1 Cache
+	// L1 Miss has occured!
+	L1D_Miss++;
+	latency += L1DCacheConf.missLatency;
 
 	// Data will be present for next access!
-	// This is executed for both read and write instructions
 	if (replaceIndex == -1)
 		replaceIndex = random() % L1DCacheConf.numSets;
 	L1DCache[replaceIndex][index].tag = tag;
 	SET_CACHELINE_VALID(L1DCache[replaceIndex][index].flags);
 
-	if (isReadAccess)
-	{
-//		 L1 Miss has occured!
-		L1D_Miss++;
-		result->cyclesConsumed += L1DCacheConf.missLatency;
-		latency += L1DCacheConf.missLatency;
-	}
-	else // Write Access, do nothing, data has been put in L1, return!
-	if (!isReadAccess)
-	{
-		L1D_Hit_Writeback++;
-		result->cyclesConsumed += L1DCacheConf.missLatency;
-		latency += L1DCacheConf.missLatency;
-		return latency;
-	}
-	// No write instructions will come here!
-
-	// Lookup in L2
 	tag = getTagFromAddress(address, L2CacheConf.tagLenBits, L2CacheConf.tagMask);
 	index = getIndexFromAddress(address, L2CacheConf.subIndexLenBits, L2CacheConf.indexMask);
 
@@ -476,10 +460,11 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 		{
 			if (L2Cache[setIndex][index].tag == tag)
 			{
-				result->cyclesConsumed += L2CacheConf.hitLatency;
 				latency += L2CacheConf.hitLatency;
-				L2_Hit_Read++;
-				result->L2Hits++;
+				if (isReadAccess)
+					L2_Hit_Read++;
+				else
+					L2_Hit_Writeback++;
 				return latency;
 			}
 		}
@@ -488,12 +473,10 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 			replaceIndex = setIndex;
 		}
 	}
-	// If here, data was not found in L2.
+
 	// L2 Miss has occured!
 	L1D_Miss--;
 	L2D_Miss++;
-	result->L2Misses++;
-	result->cyclesConsumed += L2CacheConf.missLatency;
 	latency += L2CacheConf.missLatency;
 
 	// Data will be present for next access!
@@ -502,32 +485,25 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 	L2Cache[replaceIndex][index].tag = tag;
 	SET_CACHELINE_VALID(L2Cache[replaceIndex][index].flags);
 
-	// Check for prefetch!
 	prevAccess_t *access = prevAccessList_tail;
 	for (i = 0; i < prefetch_table_entries && access != NULL; i++)
 	{
+
 		if (address == access->address + L2CacheConf.lineLenBytes)
 		{
 			//printf("0x%lx - 0x%lx\n", access->address, address);
-			if (access->sequentialAccess > 10)
+			if (access->sequentialAccess > 5)
 			{
-				result->cyclesConsumed += memReadPrefetchLatency;
 				latency += memReadPrefetchLatency;
 			}
 			insertAccess(&prevAccessList_head, &prevAccessList_tail, address, access->sequentialAccess+1);
-			result->prefetches++;
-			result->L1Hits++;
-			result->L2Misses--;
 			return latency;
 		}
 		access = access->prev;
 	}
-	// If here, data was not prefetched!
-	insertAccess(&prevAccessList_head, &prevAccessList_tail, address, 0);
 
-	// Fetch Data from the memory
-	result->cyclesConsumed += memReadLatency;
 	latency += memReadLatency;
+	insertAccess(&prevAccessList_head, &prevAccessList_tail, address, 0);
 	return latency;
 }