Major bugfix in branch_predictor, stupid me. Simple changes to cache

Signed-off-by: Gaurav Kukreja <gaurav@gauravk.in>

branch_predictor/src/branchPred.c

@@ -28,24 +28,21 @@ unsigned int bPredTableEntries;
 unsigned int prevBlockValid;
 unsigned long prevBlockEndAdd;
 
-void removeHeadEntry()
+void insertEntryToTail(bPredTableEntry_t *entry)
 {
-	// bPredTable_head and the next pointer must not be NULL
-	// TODO: Add an assert!
+//	printf("***************** Inserting Entry! 0x%lx\n\n", entry->branchInstAdd);
+
+	if (bPredTableEntries == BPRED_TABLE_MAX_ENTRIES)
+	{
+		// Table Capacity full, must remove least recently used to make space
 		bPredTableEntry_t *tmp;
 		tmp = bPredTable_head;
 		bPredTable_head = bPredTable_head->next;
 		bPredTable_head->prev = NULL;
+		bPredTableEntries--;
 		free(tmp);
-}
-
-void insertEntryToTail(bPredTableEntry_t *entry)
-{
-	if (bPredTableEntries == BPRED_TABLE_MAX_ENTRIES)
-	{
-		// Table Capacity full, must remove least recently used to make space
-
 	}
+
 	if (bPredTable_head == NULL &&
 			bPredTable_tail == NULL)
 	{
@@ -53,6 +50,7 @@ void insertEntryToTail(bPredTableEntry_t *entry)
 		entry->prev = NULL;
 		bPredTable_head = entry;
 		bPredTable_tail = entry;
+		bPredTableEntries++;
 		return;
 	}
 	else
@@ -61,6 +59,7 @@ void insertEntryToTail(bPredTableEntry_t *entry)
 		entry->prev = bPredTable_tail;
 		entry->next = NULL;
 		bPredTable_tail = entry;
+		bPredTableEntries++;
 		return;
 	}
 }
@@ -115,7 +114,12 @@ unsigned int enterBlock (unsigned long blockObjStartAdd,
 		predicted =  0;
 	}
 
+#define ADDRESS_IS_LINE_NUMBER
+#ifdef ADDRESS_IS_LINE_NUMBER
+	if (blockObjStartAdd == prevBlockEndAdd + 1)
+#else
 	if (blockObjStartAdd == prevBlockEndAdd + 4)
+#endif
 	{
 		// Branch was not taken!
 		isBranchTaken = 0;
@@ -131,6 +135,7 @@ unsigned int enterBlock (unsigned long blockObjStartAdd,
 	{
 		if (entry->branchInstAdd == prevBlockEndAdd)
 		{
+//			printf ("Entry Found!\n");
 			// Entry Found!
 			if (entry->prediction == STRONGLY_NOT_TAKEN)
 			{
@@ -201,9 +206,10 @@ unsigned int enterBlock (unsigned long blockObjStartAdd,
 	}
 	else
 	{
+//		printf ("Entry NOT Found! 0x%lx\n", prevBlockEndAdd);
 		// Entry was not found!
 		entry = malloc(sizeof(bPredTableEntry_t));
-		entry->branchInstAdd = blockObjEndAdd;
+		entry->branchInstAdd = prevBlockEndAdd;
 		if (isBranchTaken)
 		{
 			entry->prediction = WEAKLY_NOT_TAKEN;
@@ -219,10 +225,14 @@ unsigned int enterBlock (unsigned long blockObjStartAdd,
 
 	prevBlockEndAdd = blockObjEndAdd;
 
-//	if (!predicted)
-//	{
-//		printf("Branch NOT Predicted\n");
-//	}
+	if (!predicted)
+	{
+		printf("Branch NOT Predicted. Start 0x%lx; End 0x%lx\n\n", blockObjStartAdd, blockObjEndAdd);
+	}
+	else
+	{
+//		printf(" ****** Predicted. Start 0x%lx; End 0x%lx\n\n", blockObjStartAdd, blockObjEndAdd);
+	}
 
 	return predicted;
 }

cache_simulator/src/cortexA5HwMod.c

@@ -66,8 +66,8 @@ cacheLine_t **L1DCache;
 cacheLine_t **L1ICache;
 cacheLine_t **L2Cache;
 
-unsigned int memWriteLatency = 55;
-unsigned int memReadLatency = 55;
+unsigned int memWriteLatency = 50;
+unsigned int memReadLatency = 50;
 unsigned int memReadPrefetchLatency = 0;
 
 unsigned long L1D_Hit_Read = 0;
@@ -100,6 +100,9 @@ typedef struct prevAccess prevAccess_t;
 prevAccess_t *prevAccessList_head;
 prevAccess_t *prevAccessList_tail;
 
+// Round Robin L2 Cache Replacement
+unsigned int L2_RR_evictSetIndex;
+
 /**** LOCAL FUNCTIONS *********************************************************/
 
 void insertAccess(prevAccess_t **head, prevAccess_t **tail, unsigned long address, unsigned long seqAccess)
@@ -218,14 +221,14 @@ void initCacheParams ()
 
 	L1ICacheConf.isWriteThrough = 0;
 
-	L1ICacheConf.hitLatency = 1;
+	L1ICacheConf.hitLatency = 0;
 	L1ICacheConf.missLatency = 0;
 
 
 	/*** L2 Cache *****************/
 
 	L2CacheConf.lineLenBytes 		= 32;
-	L2CacheConf.cacheSizeBytes 		= 256 * 1024; // 256 KB
+	L2CacheConf.cacheSizeBytes 		= 512 * 1024; // 256 KB
 	L2CacheConf.numSets 			= 16;
 
 	L2CacheConf.numLines  			= L2CacheConf.cacheSizeBytes /
@@ -253,8 +256,8 @@ void initCacheParams ()
 
 	L2CacheConf.isWriteThrough = 0;
 
-	L2CacheConf.hitLatency = 14;
-	L2CacheConf.missLatency = 14;
+	L2CacheConf.hitLatency = 16;
+	L2CacheConf.missLatency = 16;
 }
 
 
@@ -392,7 +395,17 @@ unsigned long long cortexA5_simICache(unsigned long address,
 
 					if(l2InvalidSetIndex == -1)
 					{
-						l2InvalidSetIndex = random() % L2CacheConf.numSets;
+//						l2InvalidSetIndex = random() % L2CacheConf.numSets;
+						l2InvalidSetIndex = L2_RR_evictSetIndex++;
+						if (L2_RR_evictSetIndex == L2CacheConf.numSets)
+							L2_RR_evictSetIndex = 0;
+
+						if(IS_CACHELINE_DIRTY(L2Cache[l2Index][l2InvalidSetIndex].flags))
+						{
+							// Write Back to memory!
+							latency += memWriteLatency;
+							L2_Hit_Writeback++;
+						}
 					}
 					L2Cache[l2Index][l2InvalidSetIndex].tag = l2Tag;
 
@@ -543,7 +556,10 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 
 			if(l2InvalidSetIndex == -1)
 			{
-				l2InvalidSetIndex = random() % L2CacheConf.numSets;
+//				l2InvalidSetIndex = random() % L2CacheConf.numSets;
+				l2InvalidSetIndex = L2_RR_evictSetIndex;
+				if (L2_RR_evictSetIndex == L2CacheConf.numSets)
+					L2_RR_evictSetIndex = 0;
 
 				if(IS_CACHELINE_DIRTY(L2Cache[l2Index][l2InvalidSetIndex].flags))
 				{
@@ -586,6 +602,7 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 				 *
 				 * Add the latency.
 				 */
+
 				latency += L2CacheConf.hitLatency;
 				SET_CACHELINE_INVALID(L2Cache[index][setIndex].flags);
 				SET_CACHELINE_CLEAN(L2Cache[index][setIndex].flags);
@@ -681,6 +698,8 @@ void cortexA5_cacheSimInit(struct csim_result_t *result)
 	prevAccessList_tail = NULL;
 	prefetch_table_entries = 0;
 
+	L2_RR_evictSetIndex = 0;
+
 	return;
 }