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Commit c60903ff authored by Gaurav Kukreja's avatar Gaurav Kukreja
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ADPCM Instrumented and manually tweaked to give right performance, pushed 

Signed-off-by: Gaurav Kukreja's avatarGaurav Kukreja <gaurav@gauravk.in>
parent 9205c8c4
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Showing with 2066 additions and 61 deletions
instrument/examples/adpcm/instrumented/adpcm_IR.c
View file @ c60903ff
......@@ -274,8 +274,6 @@ memAccessCycles += simDCache((SP + outputbuffer_addr), 1);
memAccessCycles += simDCache((SP + outp_addr), 0);
*outp = (signed char) delta_37 & 15 | (signed char) outputbuffer;
outp = (uintptr_t)outp + 1;
// MANUAL!
outp_addr = outp_addr + 1;
// # SUCC: 18 [100.0%] (fallthru,exec)
adpcm_coderbb_18:
......
instrument/examples/adpcm/instrumented/my_ctop_IR.c
View file @ c60903ff
......@@ -61,6 +61,9 @@ int main() {
unsigned int ARR_SIZE_0;
unsigned long ARR_SIZE_0_addr = 0x0;
unsigned long ivtmp_34_addr = 0; // MANUAL
unsigned long ivtmp_28_addr = 0; //MANUAL
mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit();
......@@ -113,6 +116,7 @@ memAccessCycles += simICache(0x258, 20);
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45];
ivtmp_34_addr = in_Data_addr + (2 * i_45);
end_44 = end_43;
// # SUCC: 5 [100.0%] (fallthru,exec)
......@@ -124,9 +128,12 @@ memAccessCycles += simICache(0x26c, 36);
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
//Manual Annotation
memAccessCycles += simDCache(ivtmp_34_addr, 1);
i_45 = i_45 + 1;
end_44 = (long unsigned int) i_45;
ivtmp_34 = ivtmp_34 + 2;
ivtmp_34_addr = ivtmp_34_addr + 2;
if (end_44 < end_46)
goto mainbb_5;
else
......@@ -191,6 +198,7 @@ memAccessCycles += simICache(0x2f0, 28);
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i];
ivtmp_28_addr = in_Data_addr + (2 * i);
D_2229 = (int) end;
start = start_40;
// # SUCC: 10 [100.0%] (fallthru,exec)
......@@ -203,9 +211,11 @@ memAccessCycles += simICache(0x30c, 36);
// TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
memAccessCycles += simDCache(ivtmp_28_addr, 1);
i = i + 1;
start = (long unsigned int) i;
ivtmp_28 = ivtmp_28 + 2;
ivtmp_28_addr = ivtmp_28_addr + 2;
if (i != D_2229)
goto mainbb_10;
else
......
instrument/examples/adpcm/instrumented_manual/Makefile 0 → 100644
View file @ c60903ff
include ../../../../cache_simulator/Makefile.macros
include ../../../../branch_predictor/Makefile.macros
CC = gcc
CFLAGS = -O2 -std=c99
INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS)
LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB)
APP_SOURCES = my_ctop_IR.c adpcm_IR.c
all: my_ctop_IR.out
my_ctop_IR.out: $(APP_SOURCES)
$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred
check: my_ctop_IR.out
export LD_LIBRARY_PATH=$(CACHESIM_LIB)
./my_ctop_IR.out
clean:
rm -rf *.o my_ctop_IR.out
instrument/examples/adpcm/instrumented_manual/adpcm.h 0 → 100644
View file @ c60903ff
/*
** adpcm.h - include file for adpcm coder.
**
** Version 1.0, 7-Jul-92.
*/
struct adpcm_state {
short valprev; /* Previous output value */
char index; /* Index into stepsize table */
};
#ifdef __STDC__
#define ARGS(x) x
#else
#define ARGS(x) ()
#endif
void adpcm_coder (short indata[], unsigned long indata_addr, char outdata[], unsigned long outdata_addr, int len, struct adpcm_state *state, unsigned long state_addr);
instrument/examples/adpcm/instrumented_manual/adpcm_IR.c 0 → 100644
View file @ c60903ff
This diff is collapsed.
instrument/examples/adpcm/instrumented_manual/in_small.h 0 → 100644
View file @ c60903ff
This diff is collapsed.
instrument/examples/adpcm/instrumented_manual/my_ctop_IR.c 0 → 100644
View file @ c60903ff
/***********************************************************
Intermediate representation of
adpcm/app_dir/my_ctop.c
Converted by ir2c v0.1
***********************************************************/
#include <limits.h>
#include <stdint.h>
#include "ir2c.h"
#include "cacheSim.h"
#include "branchPred.h"
unsigned long SP = 0x1234;
unsigned long long memAccessCycles = 0;
unsigned long long pipelineCycles = 0;
/*
** Timing - Test timing on adpcm coder and decoder.
**
** The program creates 10Kb garbage, and runs the compressor and
** the decompressor on it.
*/
/*sds*/
#include <stdio.h>
#include "adpcm.h"
#include "in_small.h"
//#include "in_large.h"
#include "my_variables.h"
#define DATASIZE 10*1024 /* Data block size */
//ARR_SIZE is the number of short type elements in
//input data array. defined in in_data_small.h
//unsigned int ARR_SIZE = 13305601;
//unsigned int ARR_SIZE = 684433;
short int pcmdata[DATASIZE];
unsigned long pcmdata_addr = 0x14f208;
char adpcmdata[DATASIZE/2];
unsigned long adpcmdata_addr = 0x154208;
int a[123];
struct adpcm_state coder_1_state;
unsigned long coder_1_state_addr = 0x14f204;
int main() {
long unsigned int end_46;
int i_45;
long unsigned int end_44;
long unsigned int end_43;
long unsigned int start_40;
uintptr_t ivtmp_34;
int D_2229;
uintptr_t ivtmp_28;
long unsigned int count;
long unsigned int end;
long unsigned int start;
long unsigned int j;
int i;
unsigned int ARR_SIZE_0;
unsigned long ARR_SIZE_0_addr = 0x0;
unsigned long ivtmp_34_addr = 0; // MANUAL
unsigned long ivtmp_28_addr = 0; //MANUAL
mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit();
branchPred_init();
SP = SP + 0x30;
memAccessCycles += simDCache(0x354, 1); // PC Relative Load
memAccessCycles += simDCache(0x358, 1); // PC Relative Load
memAccessCycles += simDCache(ARR_SIZE_addr, 1);
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0);
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 36);
pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 7 : 0);
ARR_SIZE_0 = ARR_SIZE;
j = ARR_SIZE_0 / 10240;
if (j != 0)
goto mainbb_14;
else
goto mainbb_7;
// # SUCC: 14 [91.0%] (true,exec) 7 [9.0%] (false,exec)
mainbb_14:
// # PRED: 2 [91.0%] (true,exec)
memAccessCycles += simDCache(0x35c, 1); // PC Relative Load
memAccessCycles += simDCache((SP + 0x4), 1); // Spilling Register
memAccessCycles += simDCache(0x360, 1); // PC Relative Load
memAccessCycles += simDCache(0x364, 1); // PC Relative Load
memAccessCycles += simDCache(0x368, 1); // PC Relative Load
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x224, 40);
pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 7 : 0);
end_43 = 0;
count = 0;
// # SUCC: 3 [100.0%] (fallthru)
mainbb_3:
// # PRED: 13 [100.0%] (fallthru) 14 [100.0%] (fallthru)
pipelineCycles += 9 - (enterBlock(0xa9, 0xab) ? 7 : 0);
end_46 = end_43 + 10240;
if (end_43 < end_46)
goto mainbb_4;
else
goto mainbb_6;
// # SUCC: 4 [99.0%] (true,exec) 6 [1.0%] (false,exec)
mainbb_4:
// # PRED: 3 [99.0%] (true,exec)
memAccessCycles += simDCache((SP + 0x4), 1); // Reading Spilt Register
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x258, 20);
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45];
ivtmp_34_addr = in_Data_addr + (2 * i_45);
end_44 = end_43;
// # SUCC: 5 [100.0%] (fallthru,exec)
mainbb_5:
// # PRED: 5 [99.0%] (true,exec) 4 [100.0%] (fallthru,exec)
memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0);
// Simulating I Cache for obj block 4
memAccessCycles += simICache(0x26c, 36);
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
//Manual Annotation
memAccessCycles += simDCache(ivtmp_34_addr, 1);
i_45 = i_45 + 1;
end_44 = (long unsigned int) i_45;
ivtmp_34 = ivtmp_34 + 2;
ivtmp_34_addr = ivtmp_34_addr + 2;
if (end_44 < end_46)
goto mainbb_5;
else
goto mainbb_6;
// # SUCC: 5 [99.0%] (true,exec) 6 [1.0%] (false,exec)
mainbb_6:
// # PRED: 5 [1.0%] (false,exec) 3 [1.0%] (false,exec)
// Simulating I Cache for obj block 5
memAccessCycles += simICache(0x290, 40);
pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr);
count = count + 1;
if (j > count)
goto mainbb_13;
else
goto mainbb_7;
// # SUCC: 13 [91.0%] (true,exec) 7 [9.0%] (false,exec)
mainbb_13:
// # PRED: 6 [91.0%] (true,exec)
// Simulating I Cache for obj block 2
memAccessCycles += simICache(0x24c, 12);
end_43 = end_46;
goto mainbb_3;
// # SUCC: 3 [100.0%] (fallthru)
mainbb_7:
// # PRED: 6 [9.0%] (false,exec) 2 [9.0%] (false,exec)
memAccessCycles += simDCache(0x358, 1); // PC Relative Load
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1);
// Simulating I Cache for obj block 6
memAccessCycles += simICache(0x2b8, 32);
pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 7 : 0);
if (ARR_SIZE_0 % 10240 != 0)
goto mainbb_8;
else
goto mainbb_12;
// # SUCC: 8 [61.0%] (true,exec) 12 [39.0%] (false,exec)
mainbb_8:
// # PRED: 7 [61.0%] (true,exec)
memAccessCycles += simDCache(0x354, 1); // PC Relative Load
// Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2d8, 24);
pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
start_40 = j * 10240;
memAccessCycles += simDCache(ARR_SIZE_addr, 1);
end = ARR_SIZE;
if (start_40 < end)
goto mainbb_9;
else
goto mainbb_11;
// # SUCC: 9 [99.0%] (true,exec) 11 [1.0%] (false,exec)
mainbb_9:
// # PRED: 8 [99.0%] (true,exec)
memAccessCycles += simDCache(0x35c, 1); // PC Relative Load
memAccessCycles += simDCache(0x360, 1); // PC Relative Load
// Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2f0, 28);
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i];
ivtmp_28_addr = in_Data_addr + (2 * i);
D_2229 = (int) end;
start = start_40;
// # SUCC: 10 [100.0%] (fallthru,exec)
mainbb_10:
// # PRED: 10 [99.0%] (true,exec) 9 [100.0%] (fallthru,exec)
memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0);
// Simulating I Cache for obj block 9
memAccessCycles += simICache(0x30c, 36);
// TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
memAccessCycles += simDCache(ivtmp_28_addr, 1);
i = i + 1;
start = (long unsigned int) i;
ivtmp_28 = ivtmp_28 + 2;
ivtmp_28_addr = ivtmp_28_addr + 2;
if (i != D_2229)
goto mainbb_10;
else
goto mainbb_11;
// # SUCC: 10 [99.0%] (true,exec) 11 [1.0%] (false,exec)
mainbb_11:
// # PRED: 10 [1.0%] (false,exec) 8 [1.0%] (false,exec)
memAccessCycles += simDCache(0x360, 1); // PC Relative Load
memAccessCycles += simDCache(0x364, 1); // PC Relative Load
memAccessCycles += simDCache(0x368, 1); // PC Relative Load
// Simulating I Cache for obj block 10
memAccessCycles += simICache(0x330, 20);
pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr);
// # SUCC: 12 [100.0%] (fallthru,exec)
mainbb_12:
// # PRED: 7 [39.0%] (false,exec) 11 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 11
memAccessCycles += simICache(0x344, 16);
printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini();
pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 7 : 0);
return 0;
// # SUCC: EXIT [100.0%]
}
instrument/examples/adpcm/instrumented_manual/my_variables.h 0 → 100644
View file @ c60903ff
// unsigned int ARR_SIZE = 13305601;
unsigned int ARR_SIZE = 684433;
unsigned long ARR_SIZE_addr = 0xaa0;
instrument/examples/sha/instrumented/sha.h
View file @ c60903ff
......@@ -13,9 +13,9 @@ typedef unsigned long LONG;
#define SHA_DIGESTSIZE 20
struct SHA_INFO {
LONG digest[5]; /* message digest */
LONG count_lo, count_hi; /* 64-bit bit count */
LONG data[16]; /* SHA data buffer */
unsigned long digest[5]; /* message digest */
unsigned long count_lo, count_hi; /* 64-bit bit count */
unsigned long data[16]; /* SHA data buffer */
};
void sha_init (struct SHA_INFO *sha_info, unsigned long sha_info_addr);
......
instrument/examples/sha/instrumented/sha_IR.c
View file @ c60903ff
......@@ -57,32 +57,32 @@ unsigned long ARR_SIZE_addr = 0x55e28;
static void sha_transform (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
unsigned long A_133;
unsigned long E_132;
unsigned long D_131;
unsigned long B_130;
unsigned long A_129;
unsigned long E_128;
unsigned long D_127;
unsigned long B_126;
unsigned long A_125;
unsigned long E_124;
unsigned long E_123;
unsigned long D_122;
unsigned long D_121;
unsigned long B_120;
unsigned long B_119;
unsigned long A_118;
unsigned long A_117;
long unsigned int A_133;
long unsigned int E_132;
uintptr_t D_131;
long unsigned int B_130;
long unsigned int A_129;
long unsigned int E_128;
uintptr_t D_127;
long unsigned int B_126;
long unsigned int A_125;
long unsigned int E_124;
long unsigned int E_123;
uintptr_t D_122;
uintptr_t D_121;
long unsigned int B_120;
long unsigned int B_119;
long unsigned int A_118;
long unsigned int A_117;
uintptr_t ivtmp_116;
uintptr_t ivtmp_115;
unsigned long C_114;
unsigned long temp_113;
unsigned long C_105;
unsigned long temp_104;
unsigned long C_101;
unsigned long temp_100;
unsigned long C_97;
long unsigned int C_114;
long unsigned int temp_113;
long unsigned int C_105;
long unsigned int temp_104;
long unsigned int C_101;
long unsigned int temp_100;
long unsigned int C_97;
uintptr_t ivtmp_94;
uintptr_t ivtmp_93;
uintptr_t D_2940;
......@@ -90,14 +90,14 @@ static void sha_transform (struct SHA_INFO *sha_info, unsigned long sha_info_ad
uintptr_t ivtmp_71;
uintptr_t D_2917;
uintptr_t ivtmp_63;
unsigned long W[80];
long unsigned int W[80];
unsigned long W_addr = 0x10;
unsigned long E;
unsigned long D;
unsigned long C;
unsigned long B;
unsigned long A;
unsigned long temp;
long unsigned int E;
long unsigned int D;
long unsigned int C;
long unsigned int B;
long unsigned int A;
long unsigned int temp;
sha_transformbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
......@@ -112,12 +112,12 @@ pipelineCycles += 19 - (enterBlock(0xa4, 0xa8) ? 7 : 0);
sha_transformbb_3:
// # PRED: 3 [94.1%] (true,exec) 2 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + W_addr + (4 * (+ivtmp_93))), 0);
memAccessCycles += simDCache((SP + W_addr + (+ivtmp_93)), 0);
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x244, 28);
// TODO: UnmappedLS: Load GlobalVar sha_info at line 170
pipelineCycles += 12 - (enterBlock(0xa9, 0xaf) ? 7 : 0);
*(unsigned long*)((uintptr_t)&W + (uintptr_t)ivtmp_93) = *(unsigned long*)((uintptr_t)ivtmp_94 + 28);
*(long unsigned int*)((uintptr_t)&W + (uintptr_t)ivtmp_93) = *(long unsigned int*)((uintptr_t)ivtmp_94 + 28);
ivtmp_93 = ivtmp_93 + 4;
ivtmp_94 = ivtmp_94 + 4;
if (ivtmp_93 != 64)
......@@ -146,7 +146,7 @@ memAccessCycles += simICache(0x268, 44);
// TODO: UnmappedLS: Load LocalVar W at line 183
// TODO: UnmappedLS: Store LocalVar W at line 185
pipelineCycles += 23 - (enterBlock(0xb2, 0xbc) ? 7 : 0);
*(unsigned long*)((uintptr_t)ivtmp_79 + 12) = ((*(unsigned long*)((uintptr_t)ivtmp_79 + (int)4294967276) ^ *(unsigned long*)((uintptr_t)ivtmp_79)) ^ *(unsigned long*)((uintptr_t)ivtmp_79 + (int)4294967252)) ^ *(unsigned long*)((uintptr_t)ivtmp_79 + (int)4294967244);
*(long unsigned int*)((uintptr_t)ivtmp_79 + 12) = ((*(long unsigned int*)((uintptr_t)ivtmp_79 + (int)4294967276) ^ *(long unsigned int*)((uintptr_t)ivtmp_79)) ^ *(long unsigned int*)((uintptr_t)ivtmp_79 + (int)4294967252)) ^ *(long unsigned int*)((uintptr_t)ivtmp_79 + (int)4294967244);
ivtmp_79 = ivtmp_79 + 4;
if (ivtmp_79 != D_2940)
goto sha_transformbb_5;
......@@ -192,7 +192,7 @@ sha_transformbb_7:
memAccessCycles += simICache(0x2d8, 48);
// TODO: UnmappedLS: Load LocalVar W at line 206
pipelineCycles += 16 - (enterBlock(0xce, 0xd9) ? 7 : 0);
temp = (((*(unsigned long*)((uintptr_t)&W + (uintptr_t)ivtmp_71) + 1518500249) + E) + ((A_133<<27)|(A_133>>(sizeof(A_133)*CHAR_BIT-27)))) + (~B & D | C & B);
temp = (((*(long unsigned int*)((uintptr_t)&W + (uintptr_t)ivtmp_71) + 1518500249) + E) + ((A_133<<27)|(A_133>>(sizeof(A_133)*CHAR_BIT-27)))) + (~B & D | C & B);
C_97 = (B<<2)|(B>>(sizeof(B)*CHAR_BIT-2));
ivtmp_71 = ivtmp_71 + 4;
if (ivtmp_71 != 80)
......@@ -234,7 +234,7 @@ sha_transformbb_9:
memAccessCycles += simICache(0x330, 44);
// TODO: UnmappedLS: Load LocalVar W at line 228
pipelineCycles += 17 - (enterBlock(0xe4, 0xee) ? 7 : 0);
temp_100 = (((*(unsigned long*)((uintptr_t)ivtmp_116 + 80) + 1859775393) + E_132) + ((A_129<<27)|(A_129>>(sizeof(A_129)*CHAR_BIT-27)))) + ((C_97 ^ B_130) ^ D_131);
temp_100 = (((*(long unsigned int*)((uintptr_t)ivtmp_116 + 80) + 1859775393) + E_132) + ((A_129<<27)|(A_129>>(sizeof(A_129)*CHAR_BIT-27)))) + ((C_97 ^ B_130) ^ D_131);
C_101 = (B_130<<2)|(B_130>>(sizeof(B_130)*CHAR_BIT-2));
ivtmp_116 = ivtmp_116 + 4;
if (ivtmp_116 != D_2917)
......@@ -288,7 +288,7 @@ sha_transformbb_10:
memAccessCycles += simICache(0x384, 52);
// TODO: UnmappedLS: Load LocalVar W at line 249
pipelineCycles += 18 - (enterBlock(0xf9, 0x105) ? 7 : 0);
temp_104 = (((*(unsigned long*)((uintptr_t)ivtmp_115 + 160) + (int)2400959708) + E_128) + ((A_125<<27)|(A_125>>(sizeof(A_125)*CHAR_BIT-27)))) + ((D_127 | C_101) & B_126 | D_127 & C_101);
temp_104 = (((*(long unsigned int*)((uintptr_t)ivtmp_115 + 160) + (int)2400959708) + E_128) + ((A_125<<27)|(A_125>>(sizeof(A_125)*CHAR_BIT-27)))) + ((D_127 | C_101) & B_126 | D_127 & C_101);
C_105 = (B_126<<2)|(B_126>>(sizeof(B_126)*CHAR_BIT-2));
ivtmp_115 = ivtmp_115 + 4;
if (ivtmp_115 != D_2917)
......@@ -315,7 +315,7 @@ sha_transformbb_11:
memAccessCycles += simICache(0x3d8, 44);
// TODO: UnmappedLS: Load LocalVar W at line 270
pipelineCycles += 17 - (enterBlock(0x10e, 0x118) ? 7 : 0);
temp_113 = (((*(unsigned long*)((uintptr_t)ivtmp_63 + 240) + (int)3395469782) + E_123) + ((A_117<<27)|(A_117>>(sizeof(A_117)*CHAR_BIT-27)))) + ((C_105 ^ B_119) ^ D_121);
temp_113 = (((*(long unsigned int*)((uintptr_t)ivtmp_63 + 240) + (int)3395469782) + E_123) + ((A_117<<27)|(A_117>>(sizeof(A_117)*CHAR_BIT-27)))) + ((C_105 ^ B_119) ^ D_121);
C_114 = (B_119<<2)|(B_119>>(sizeof(B_119)*CHAR_BIT-2));
ivtmp_63 = ivtmp_63 + 4;
if (ivtmp_63 != D_2917)
......@@ -432,10 +432,10 @@ pipelineCycles += 16 - (enterBlock(0x1e8, 0x1f2) ? 7 : 0);
void sha_final (struct SHA_INFO *sha_info, unsigned long sha_info_addr) {
int count_203;
unsigned long hi_bit_count;
unsigned long lo_bit_count;
long unsigned int hi_bit_count;
long unsigned int lo_bit_count;
int count;
unsigned long * D_2805;
long unsigned int * D_2805;
sha_finalbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
......@@ -502,10 +502,10 @@ void sha_update (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsign
uintptr_t ivtmp_232;
int D_3089;
uintptr_t D_3086;
unsigned long * D_2795;
long unsigned int * D_2795;
long unsigned int D_2787;
long unsigned int count_1;
unsigned long D_2785;
long unsigned int D_2785;
sha_updatebb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
......@@ -566,7 +566,7 @@ memAccessCycles += simICache(0x524, 44);
pipelineCycles += 15 - (enterBlock(0x165, 0x16f) ? 7 : 0);
D_3103 = ivtmp_232 + (uintptr_t)buffer;
memAccessCycles += simDCache(buffer_addr, 1);
my_memcpy (D_2795, sha_info_addr, D_3103, buffer_addr + (unsigned long) ivtmp_232, 64);
my_memcpy (D_2795, sha_info_addr, D_3103, buffer_addr + ivtmp_232, 64);
sha_transform (sha_info, sha_info_addr);
ivtmp_232 = ivtmp_232 + 64;
if ((int) (count_1 - ivtmp_232) > 63)
......@@ -602,17 +602,17 @@ pipelineCycles += 20 - (enterBlock(0x178, 0x17e) ? 7 : 0);
void sha_stream (struct SHA_INFO *sha_info, unsigned long sha_info_addr, unsigned char *inData, unsigned long inData_addr, unsigned long int dSize) {
unsigned long end_289;
unsigned long end_288;
long unsigned int end_289;
long unsigned int end_288;
uintptr_t ivtmp_273;
uintptr_t D_3143;
uintptr_t ivtmp_267;
unsigned char data[8192];
unsigned long data_addr;
unsigned long count;
unsigned long end;
unsigned long start;
unsigned long j;
unsigned long data_addr = 0x1fdfb8;
long unsigned int count;
long unsigned int end;
long unsigned int start;
long unsigned int j;
unsigned int ARR_SIZE_4;
sha_streambb_2:
......@@ -740,7 +740,7 @@ memAccessCycles += simICache(0x6d8, 20);
// TODO: UnmappedLS: Load GlobalVar in_Data at line 470
pipelineCycles += 11 - (enterBlock(0x1d6, 0x1da) ? 7 : 0);
*(unsigned char*)((uintptr_t)&data + (uintptr_t)ivtmp_267) = *(unsigned char *)((uintptr_t)inData + start + (uintptr_t)ivtmp_267);
memAccessCycles += simDCache(inData_addr + (sizeof(unsigned char *) * (+start+ivtmp_267)), 1);
memAccessCycles += simDCache(inData_addr + (+start+ivtmp_267), 1);
ivtmp_267 = ivtmp_267 + 1;
if (ivtmp_267 != D_3143)
goto sha_streambb_9;
......
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