Commit before adding power related code to instrument.py

Signed-off-by: Gaurav Kukreja <gaurav@gauravk.in>

cache_simulator/Makefile

@@ -14,4 +14,4 @@ cacheSim:
 	
 clean:
 	rm -rf *.o
-	rm -rf $(LIB)/cacheSim.so
+	rm -rf $(LIB)/libcacheSim.so

cache_simulator/src/cortexA5HwMod.c

@@ -66,9 +66,9 @@ cacheLine_t **L1DCache;
 cacheLine_t **L1ICache;
 cacheLine_t **L2Cache;
 
-unsigned int memWriteLatency = 200;
-unsigned int memReadLatency = 200;
-unsigned int memReadPrefetchLatency = 0;
+unsigned int memWriteLatency = 80;
+unsigned int memReadLatency = 80;
+unsigned int memReadPrefetchLatency = 15;
 
 unsigned long L1D_Hit_Read = 0;
 unsigned long L1D_Hit_Writeback = 0;
@@ -218,8 +218,8 @@ void initCacheParams ()
 
 	L1ICacheConf.isWriteThrough = 0;
 
-	L1ICacheConf.hitLatency = 0;
-	L1ICacheConf.missLatency = 0;
+	L1ICacheConf.hitLatency = 1;
+	L1ICacheConf.missLatency = 1;
 
 
 	/*** L2 Cache *****************/
@@ -429,7 +429,10 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 			{
 				latency += L1DCacheConf.hitLatency;
 				if (isReadAccess)
+				{
 					L1D_Hit_Read++;
+					result->L1Hits++;
+				}
 				else
 					L1D_Hit_Writeback++;
 				return latency;
@@ -462,7 +465,10 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 			{
 				latency += L2CacheConf.hitLatency;
 				if (isReadAccess)
+				{
 					L2_Hit_Read++;
+					result->L2Hits++;
+				}
 				else
 					L2_Hit_Writeback++;
 				return latency;
@@ -477,6 +483,7 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 	// L2 Miss has occured!
 	L1D_Miss--;
 	L2D_Miss++;
+	result->L2Misses++;
 	latency += L2CacheConf.missLatency;
 
 	// Data will be present for next access!
@@ -485,6 +492,8 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 	L2Cache[replaceIndex][index].tag = tag;
 	SET_CACHELINE_VALID(L2Cache[replaceIndex][index].flags);
 
+	if(isReadAccess)
+	{
 		prevAccess_t *access = prevAccessList_tail;
 		for (i = 0; i < prefetch_table_entries && access != NULL; i++)
 		{
@@ -492,18 +501,22 @@ unsigned long long cortexA5_simDCache(unsigned long address,
 			if (address == access->address + L2CacheConf.lineLenBytes)
 			{
 				//printf("0x%lx - 0x%lx\n", access->address, address);
-			if (access->sequentialAccess > 5)
+				if (access->sequentialAccess > 15)
 				{
 					latency += memReadPrefetchLatency;
+					result->prefetches++;
+					result->L1Hits++;
+					result->L2Misses--;
 				}
 				insertAccess(&prevAccessList_head, &prevAccessList_tail, address, access->sequentialAccess+1);
 				return latency;
 			}
 			access = access->prev;
 		}
+		insertAccess(&prevAccessList_head, &prevAccessList_tail, address, 0);
+	}
 
 	latency += memReadLatency;
-	insertAccess(&prevAccessList_head, &prevAccessList_tail, address, 0);
 	return latency;
 }
 

examples/Makefile

@@ -5,7 +5,7 @@ include Makefile.macros
 #EXAMPLES = adpcm 
 #EXAMPLES = sha sieve
 #EXAMPLES = basicmath 
-EXAMPLES = test_memory 
+EXAMPLES = sieve 
 STARTADR = 0x10000214
 
 # Space separated list of all C files in APPDIR

instrument/examples/adpcm/instrumented/adpcm_IR.c

@@ -101,6 +101,7 @@ void  adpcm_coder (short indata[], unsigned long indata_addr, char outdata[], un
   uintptr_t ivtmp_28;
   int bufferstep;
   int outputbuffer;
+  unsigned long outputbuffer_addr = 0x8;
   int index;
   int vpdiff;
   int valpred;
@@ -109,6 +110,7 @@ void  adpcm_coder (short indata[], unsigned long indata_addr, char outdata[], un
   int delta;
   int sign;
   signed char * outp;
+  unsigned long outp_addr = 0x0;
 
 adpcm_coderbb_2:
 //  # PRED: ENTRY [100.0%]  (fallthru,exec)
@@ -136,13 +138,13 @@ pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 7 : 0);
 
 adpcm_coderbb_3:
 //  # PRED: 2 [91.0%]  (true,exec)
-memAccessCycles += simDCache((SP + 0x0), 1, &csim_result);  // Spilling Register
 memAccessCycles += simDCache(0x4a8, 1, &csim_result);  // PC Relative Load
+memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
 // Simulating I Cache for obj block 1
 memAccessCycles += simICache(0x398, 32, &csim_result);
 pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
   outp =  outdata;
-  memAccessCycles += simDCache(outdata_addr, 1, &csim_result);
+//  memAccessCycles += simDCache(outdata_addr, 1, &csim_result);
   ivtmp_28 = 0;
   bufferstep = 1;
 //  # SUCC: 4 [100.0%]  (fallthru,exec)
@@ -150,10 +152,6 @@ pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
 adpcm_coderbb_4:
 //  # PRED: 18 [91.0%]  (true,exec) 3 [100.0%]  (fallthru,exec)
 memAccessCycles += simDCache((SP + 0x4), 1, &csim_result);  // Reading Spilt Register
-memAccessCycles += simDCache((SP + 0x8), 1, &csim_result);  // Spilling Register
-memAccessCycles += simDCache((SP + 0x8), 1, &csim_result);  // Reading Spilt Register
-memAccessCycles += simDCache((SP + 0x0), 1, &csim_result);  // Reading Spilt Register
-memAccessCycles += simDCache((SP + 0x0), 1, &csim_result);  // Spilling Register
 pipelineCycles += 48 - (enterBlock(0x106, 0x137) ? 7 : 0);
   diff = (int) *(short int *)((uintptr_t)indata + (uintptr_t)ivtmp_28) - valpred;
   memAccessCycles += simDCache(indata_addr + (+ivtmp_28), 1, &csim_result);
@@ -266,13 +264,18 @@ adpcm_coderbb_15:
 
 adpcm_coderbb_16:
 //  # PRED: 15 [50.0%]  (true,exec)
+memAccessCycles += simDCache((SP + outputbuffer_addr), 0, &csim_result);
   outputbuffer = delta_37 << 4 & 255;
   goto adpcm_coderbb_18;
 //  # SUCC: 18 [100.0%]  (fallthru,exec)
 
 adpcm_coderbb_17:
 //  # PRED: 15 [50.0%]  (false,exec)
+memAccessCycles += simDCache((SP + outputbuffer_addr), 1, &csim_result);
+memAccessCycles += simDCache(outdata_addr + (unsigned long)((uintptr_t)outp - (uintptr_t)outdata), 0, &csim_result); //MANUAL
+//memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
   *outp =  (signed char) delta_37 & 15 | (signed char) outputbuffer;
+  memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
   outp = (uintptr_t)outp + 1;
 //  # SUCC: 18 [100.0%]  (fallthru,exec)
 
@@ -280,8 +283,9 @@ adpcm_coderbb_18:
 //  # PRED: 16 [100.0%]  (fallthru,exec) 17 [100.0%]  (fallthru,exec)
 // Simulating I Cache for obj block 2
 memAccessCycles += simICache(0x3b8, 200, &csim_result);
-// TODO: UnmappedLS: Store GlobalVar adpcmdata at line 306
 // TODO: UnmappedLS: Load GlobalVar pcmdata at line 263
+// TODO: UnmappedLS: Load LocalVar outp at line 305
+// TODO: UnmappedLS: Store GlobalVar pcmdata at line 306
   bufferstep = bufferstep == 0;
   len = len + -1;
   ivtmp_28 = ivtmp_28 + 2;
@@ -293,8 +297,6 @@ memAccessCycles += simICache(0x3b8, 200, &csim_result);
 
 adpcm_coderbb_19:
 //  # PRED: 18 [9.0%]  (false,exec)
-memAccessCycles += simDCache((SP + 0x8), 1, &csim_result);  // Reading Spilt Register
-memAccessCycles += simDCache((SP + 0x0), 1, &csim_result);  // Reading Spilt Register
 pipelineCycles += 10 - (enterBlock(0x138, 0x13b) ? 7 : 0);
   if (bufferstep == 0)
     goto adpcm_coderbb_20;
@@ -304,6 +306,7 @@ pipelineCycles += 10 - (enterBlock(0x138, 0x13b) ? 7 : 0);
 
 adpcm_coderbb_20:
 //  # PRED: 19 [67.0%]  (true,exec)
+memAccessCycles += simDCache((SP + outputbuffer_addr), 1, &csim_result);
   *outp = (signed char) (signed char) outputbuffer;
 //  # SUCC: 21 [100.0%]  (fallthru,exec)
 
@@ -311,7 +314,8 @@ adpcm_coderbb_21:
 //  # PRED: 19 [33.0%]  (false,exec) 20 [100.0%]  (fallthru,exec) 2 [9.0%]  (false,exec)
 // Simulating I Cache for obj block 3
 memAccessCycles += simICache(0x480, 16, &csim_result);
-// TODO: UnmappedLS: Store GlobalVar adpcmdata at line 315
+// TODO: UnmappedLS: Load LocalVar outp at line 314
+// TODO: UnmappedLS: Store GlobalVar stepsizeTable at line 315
 memAccessCycles += simDCache((SP + 0xc), 1, &csim_result);  // Reading Spilt Register
 // Simulating I Cache for obj block 4
 memAccessCycles += simICache(0x490, 24, &csim_result);

instrument/examples/adpcm/instrumented/my_ctop_IR.c

@@ -10,7 +10,7 @@
 #include "ir2c.h"
 #include "cacheSim.h"
 #include "branchPred.h"
-unsigned long SP = 0x1234;
+unsigned long SP = 0x1fffb8;
 unsigned long long memAccessCycles = 0;
 unsigned long long pipelineCycles = 0;
 struct csim_result_t csim_result;
@@ -60,6 +60,10 @@ int main() {
   long unsigned int j;
   int i;
   unsigned int ARR_SIZE_0;
+  unsigned long ARR_SIZE_0_addr = 0x0;
+
+  unsigned long ivtmp_34_addr = 0; // MANUAL                                                                 
+  unsigned long ivtmp_28_addr = 0; 
 
 mainbb_2:
 //  # PRED: ENTRY [100.0%]  (fallthru,exec)
@@ -67,9 +71,9 @@ cacheSimInit(&csim_result);
 branchPred_init();
 SP = SP + 0x30;
 memAccessCycles += simDCache(0x354, 1, &csim_result);  // PC Relative Load
-memAccessCycles += simDCache((SP + 0x0), 1, &csim_result);  // Spilling Register
 memAccessCycles += simDCache(0x358, 1, &csim_result);  // PC Relative Load
 memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
+memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0, &csim_result);
 // Simulating I Cache for obj block 0
 memAccessCycles += simICache(0x200, 36, &csim_result);
 pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 7 : 0);
@@ -113,6 +117,7 @@ memAccessCycles += simICache(0x258, 20, &csim_result);
 pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
   i_45 = (int) end_43;
   ivtmp_34 = (uintptr_t)&in_Data[i_45];
+  ivtmp_34_addr = in_Data_addr + (2 * i_45); 
   end_44 = end_43;
 //  # SUCC: 5 [100.0%]  (fallthru,exec)
 
@@ -124,9 +129,11 @@ memAccessCycles += simICache(0x26c, 36, &csim_result);
 // TODO: UnmappedLS: Load GlobalVar in_Data at line 179
 pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
   pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
+  memAccessCycles += simDCache(ivtmp_34_addr, 1, &csim_result);
   i_45 = i_45 + 1;
   end_44 = (long unsigned int) i_45;
   ivtmp_34 = ivtmp_34 + 2;
+  ivtmp_34_addr = ivtmp_34_addr + 2;
   if (end_44 < end_46)
     goto mainbb_5;
   else
@@ -157,7 +164,7 @@ memAccessCycles += simICache(0x24c, 12, &csim_result);
 mainbb_7:
 //  # PRED: 6 [9.0%]  (false,exec) 2 [9.0%]  (false,exec)
 memAccessCycles += simDCache(0x358, 1, &csim_result);  // PC Relative Load
-memAccessCycles += simDCache((SP + 0x0), 1, &csim_result);  // Reading Spilt Register
+memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1, &csim_result);
 // Simulating I Cache for obj block 6
 memAccessCycles += simICache(0x2b8, 32, &csim_result);
 pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 7 : 0);
@@ -191,6 +198,7 @@ memAccessCycles += simICache(0x2f0, 28, &csim_result);
 pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
   i = (int) start_40;
   ivtmp_28 = (uintptr_t)&in_Data[i];
+  ivtmp_28_addr = in_Data_addr + (2 * i);
   D_2229 = (int) end;
   start = start_40;
 //  # SUCC: 10 [100.0%]  (fallthru,exec)
@@ -202,10 +210,12 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0, &csim_res
 memAccessCycles += simICache(0x30c, 36, &csim_result);
 // TODO: UnmappedLS: Inaccurately Matched Load at line 219
 pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
+  memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result);
   pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
   i = i + 1;
   start = (long unsigned int) i;
   ivtmp_28 = ivtmp_28 + 2;
+  ivtmp_28_addr = ivtmp_28_addr + 2;
   if (i != D_2229)
     goto mainbb_10;
   else

instrument/examples/sieve/instrumented/erat_sieve_no_print_IR.c

@@ -40,10 +40,11 @@ void sieve_func() {
   uintptr_t D_2240;
   uintptr_t D_2230;
   uintptr_t ivtmp_36;
-  unsigned long ivtmp_36_addr;
+  unsigned long ivtmp_36_addr; //MANUAL
   int j;
   int i;
   unsigned int sieve[500000];
+  unsigned long sieve_addr = 0x0;
 
 sieve_funcbb_2:
 //  # PRED: ENTRY [100.0%]  (fallthru,exec)
@@ -57,12 +58,12 @@ pipelineCycles += 24 - (enterBlock(0x96, 0x9f) ? 7 : 0);
 
 sieve_funcbb_3:
 //  # PRED: 3 [99.0%]  (true,exec) 2 [100.0%]  (fallthru,exec)
-memAccessCycles += simDCache((SP + 0x0), 1, &csim_result);  // Spilling Register
 memAccessCycles += simDCache(results_addr + (+ivtmp_68), 0, &csim_result);
 // Simulating I Cache for obj block 1
 memAccessCycles += simICache(0x228, 28, &csim_result);
 pipelineCycles += 13 - (enterBlock(0xa0, 0xa6) ? 7 : 0);
   *(unsigned int*)((uintptr_t)&results + (uintptr_t)ivtmp_68) = 0;
+  memAccessCycles += simDCache((SP + sieve_addr + (+ivtmp_68)), 0, &csim_result);
   *(unsigned int*)((uintptr_t)&sieve + (uintptr_t)ivtmp_68) = 1;
   ivtmp_68 = ivtmp_68 + 4;
   if (ivtmp_68 != 2000000)
@@ -83,11 +84,11 @@ pipelineCycles += 21 - (enterBlock(0xa7, 0xb3) ? 7 : 0);
 
 sieve_funcbb_4:
 //  # PRED: 7 [99.0%]  (true,exec) 17 [100.0%]  (fallthru)
-memAccessCycles += simDCache((SP + 0x0), 1, &csim_result);  // Reading Spilt Register
 // Simulating I Cache for obj block 3
 memAccessCycles += simICache(0x278, 16, &csim_result);
 pipelineCycles += 9 - (enterBlock(0xb4, 0xb7) ? 7 : 0);
   D_2263 = (unsigned int) i_72;
+  memAccessCycles += simDCache((SP + sieve_addr + (+D_2263*4)), 1, &csim_result);
   if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2263 * 4) != 0)
     goto sieve_funcbb_5;
   else
@@ -116,7 +117,7 @@ pipelineCycles += 8 - (enterBlock(0xbb, 0xbb) ? 7 : 0);
 
 sieve_funcbb_6:
 //  # PRED: 6 [91.0%]  (true,exec) 18 [100.0%]  (fallthru)
-memAccessCycles += simDCache((SP + 0x4), 1, &csim_result);  // Spilling Register
+memAccessCycles += simDCache((SP + sieve_addr + (4 * (j_76))), 0, &csim_result);
 // Simulating I Cache for obj block 6
 memAccessCycles += simICache(0x298, 40, &csim_result);
 pipelineCycles += 17 - (enterBlock(0xbc, 0xc5) ? 7 : 0);
@@ -156,9 +157,9 @@ pipelineCycles += 13 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
 
 sieve_funcbb_9:
 //  # PRED: 11 [99.0%]  (true,exec) 8 [100.0%]  (fallthru,exec)
-memAccessCycles += simDCache((SP + 0x0), 1, &csim_result);  // Reading Spilt Register
 pipelineCycles += 12 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
   D_2240 = (unsigned int) j;
+  memAccessCycles += simDCache((SP + sieve_addr + (+D_2240*4)), 1, &csim_result);
   if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2240 * 4) != 0)
     goto sieve_funcbb_10;
   else
@@ -212,7 +213,7 @@ sieve_funcbb_14:
 memAccessCycles += simICache(0x328, 12, &csim_result);
 // TODO: UnmappedLS: Load GlobalVar results at line 224
 pipelineCycles += 8 - (enterBlock(0xe0, 0xe2) ? 7 : 0);
-  memAccessCycles += simDCache(ivtmp_36_addr + 4, 1, &csim_result);
+memAccessCycles += simDCache(ivtmp_36_addr + 4, 1, &csim_result);
   if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0)
     goto sieve_funcbb_16;
   else

instrument/examples/sieve/manually_instrumented/erat_sieve_no_print_IR.c

-/***********************************************************
- Intermediate representation of
-    sieve/app_dir/erat_sieve_no_print.c
-
- Converted by ir2c v0.1
-
- ***********************************************************/
-#include <limits.h>
-#include <stdint.h>
-#include "ir2c.h"
-
-#include <stdio.h>
-
-#define N 500000
-
-unsigned int results[N];
-
-unsigned long SP = 0x1234;
-
-struct test {
-  unsigned int v;
-  unsigned int k;
-} m = { 1, 1 };
-unsigned long m_addr = 0x7c8;
-
-void sieve_func() {
-  int j_76;
-  uintptr_t ivtmp_74;
-  int i_72;
-  uintptr_t ivtmp_68;
-  uintptr_t D_2263;
-  uintptr_t ivtmp_58;
-  uintptr_t D_2252;
-  uintptr_t ivtmp_49;
-  uintptr_t D_2240;
-  uintptr_t D_2230;
-  uintptr_t ivtmp_36;
-  int j;
-  int i;
-  unsigned int sieve[500000];
-
-sieve_funcbb_2:
-//  # PRED: ENTRY [100.0%]  (fallthru,exec)
-  ivtmp_68 = 0;
-//  # SUCC: 3 [100.0%]  (fallthru,exec)
-
-sieve_funcbb_3:
-//  # PRED: 3 [99.0%]  (true,exec) 2 [100.0%]  (fallthru,exec)
-  *(unsigned int*)((uintptr_t)&results + (uintptr_t)ivtmp_68) = 0;
-  *(unsigned int*)((uintptr_t)&sieve + (uintptr_t)ivtmp_68) = 1;
-  ivtmp_68 = ivtmp_68 + 4;
-  if (ivtmp_68 != 2000000)
-    goto sieve_funcbb_3;
-  else
-    goto sieve_funcbb_17;
-//  # SUCC: 3 [99.0%]  (true,exec) 17 [1.0%]  (false,exec)
-
-sieve_funcbb_17:
-//  # PRED: 3 [1.0%]  (false,exec)
-  ivtmp_49 = 6;
-  ivtmp_58 = 4;
-  i_72 = 2;
-//  # SUCC: 4 [100.0%]  (fallthru)
-
-sieve_funcbb_4:
-//  # PRED: 7 [99.0%]  (true,exec) 17 [100.0%]  (fallthru)
-  D_2263 = (unsigned int) i_72;
-  if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2263 * 4) != 0)
-    goto sieve_funcbb_5;
-  else
-    goto sieve_funcbb_7;
-//  # SUCC: 5 [50.0%]  (true,exec) 7 [50.0%]  (false,exec)
-
-sieve_funcbb_5:
-//  # PRED: 4 [50.0%]  (true,exec)
-  j_76 = (int) ivtmp_58;
-  if (j_76 <= 499999)
-    goto sieve_funcbb_18;
-  else
-    goto sieve_funcbb_7;
-//  # SUCC: 18 [91.0%]  (true,exec) 7 [9.0%]  (false,exec)
-
-sieve_funcbb_18:
-//  # PRED: 5 [91.0%]  (true,exec)
-  ivtmp_74 = ivtmp_49;
-//  # SUCC: 6 [100.0%]  (fallthru)
-
-sieve_funcbb_6:
-//  # PRED: 6 [91.0%]  (true,exec) 18 [100.0%]  (fallthru)
-  sieve[j_76] = 0;
-  D_2252 = (unsigned int) j_76 + D_2263;
-  j_76 = (int) D_2252;
-  ivtmp_74 = D_2263 + ivtmp_74;
-  if ((int) (ivtmp_74 - D_2263) <= 499999)
-    goto sieve_funcbb_6;
-  else
-    goto sieve_funcbb_7;
-//  # SUCC: 6 [91.0%]  (true,exec) 7 [9.0%]  (false,exec)
-
-sieve_funcbb_7:
-//  # PRED: 4 [50.0%]  (false,exec) 6 [9.0%]  (false,exec) 5 [9.0%]  (false,exec)
-  i_72 = i_72 + 1;
-  ivtmp_58 = ivtmp_58 + 2;
-  ivtmp_49 = ivtmp_49 + 3;
-  if (i_72 * i_72 <= 499999)
-    goto sieve_funcbb_4;
-  else
-    goto sieve_funcbb_8;
-//  # SUCC: 4 [99.0%]  (true,exec) 8 [1.0%]  (false,exec)
-
-sieve_funcbb_8:
-//  # PRED: 7 [1.0%]  (false,exec)
-  j = 2;
-  i = 0;
-//  # SUCC: 9 [100.0%]  (fallthru,exec)
-
-sieve_funcbb_9:
-//  # PRED: 11 [99.0%]  (true,exec) 8 [100.0%]  (fallthru,exec)
-  D_2240 = (unsigned int) j;
-  if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2240 * 4) != 0)
-    goto sieve_funcbb_10;
-  else
-    goto sieve_funcbb_11;
-//  # SUCC: 10 [50.0%]  (true,exec) 11 [50.0%]  (false,exec)
-
-sieve_funcbb_10:
-//  # PRED: 9 [50.0%]  (true,exec)
-  results[i] = D_2240;
-  i = i + 1;
-//  # SUCC: 11 [100.0%]  (fallthru,exec)
-
-sieve_funcbb_11:
-//  # PRED: 9 [50.0%]  (false,exec) 10 [100.0%]  (fallthru,exec)
-  j = j + 1;
-  if (j != 500000)
-    goto sieve_funcbb_9;
-  else
-    goto sieve_funcbb_12;
-//  # SUCC: 9 [99.0%]  (true,exec) 12 [1.0%]  (false,exec)
-
-sieve_funcbb_12:
-//  # PRED: 11 [1.0%]  (false,exec)
-  if (results[0] == 0)
-    goto sieve_funcbb_16;
-  else
-    goto sieve_funcbb_13;
-//  # SUCC: 16 [4.5%]  (true,exec) 13 [95.5%]  (false,exec)
-
-sieve_funcbb_13:
-//  # PRED: 12 [95.5%]  (false,exec)
-  ivtmp_36 = (uintptr_t)&results;
-  D_2230 = ivtmp_36 + 1999996;
-//  # SUCC: 14 [100.0%]  (fallthru,exec)
-
-sieve_funcbb_14:
-//  # PRED: 15 [98.9%]  (true,exec) 13 [100.0%]  (fallthru,exec)
-  if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0)
-    goto sieve_funcbb_16;
-  else
-    goto sieve_funcbb_15;
-//  # SUCC: 16 [4.5%]  (true,exec) 15 [95.5%]  (false,exec)
-
-sieve_funcbb_15:
-//  # PRED: 14 [95.5%]  (false,exec)
-  ivtmp_36 = ivtmp_36 + 4;
-  if (ivtmp_36 != D_2230)
-    goto sieve_funcbb_14;
-  else
-    goto sieve_funcbb_16;
-//  # SUCC: 14 [98.9%]  (true,exec) 16 [1.1%]  (false,exec)
-
-sieve_funcbb_16:
-//  # PRED: 14 [4.5%]  (true,exec) 15 [1.1%]  (false,exec) 12 [4.5%]  (true,exec)
-  m.v = 0;
-  return;
-//  # SUCC: EXIT [100.0%] 
-
-}
-
-
-
-int main(void) {
-mainbb_2:
-//  # PRED: ENTRY [100.0%]  (fallthru,exec)
-  sieve_func ();
-  return 0;
-//  # SUCC: EXIT [100.0%] 
-
-}
-
-

instrument/gdb_info.py

@@ -53,15 +53,6 @@ def debugListVariables(listVariables):
     print ""
 
 
-def gdbxFilePrefix(file):
-    file.write("python\n")
-    file.write("def exe(arg):\n")
-    file.write("\ttry:\n")
-    file.write("\t\tgdb.execute (arg)\n")
-    file.write("\texcept:\n")
-    file.write("\t\tpass\n")
-    file.write("\tpass\n")
-
 # class GlobalVariable:
 #     def __init__(self):
 #         self.name = ""
@@ -238,7 +229,6 @@ def getLocalVariablesForAllFunc(listBinaryFileNames, listFunctionsObj):
         gdbOFileName = "/tmp/" + func.functionName + ".lVarName.gdbo"
         
         gdbXFile = open(gdbXFileName, 'w')
-#         gdbxFilePrefix(gdbXFile)
         gdbXFile.write("target sim\n")
         gdbXFile.write("load\n")
         gdbXFile.write("b %s\n" % func.functionName)
@@ -286,7 +276,6 @@ def getLocalVariablesForAllFunc(listBinaryFileNames, listFunctionsObj):
         gdbOFile.close()
         
         gdbXFile = open(gdbXFileName, 'w')
-#         gdbxFilePrefix(gdbXFile)
         gdbXFile.write("target sim\n")
         gdbXFile.write("load\n")
         gdbXFile.write("info scope %s\n" % func.functionName)
@@ -314,21 +303,20 @@ def getLocalVariablesForAllFunc(listBinaryFileNames, listFunctionsObj):
         gdbOFile.close()
         
         gdbXFile = open(gdbXFileName, 'w')
-        gdbxFilePrefix(gdbXFile)
-        gdbXFile.write('exe("target sim")\n')
-        gdbXFile.write('exe("load")\n')
-        gdbXFile.write('exe("b %s")\n' % func.functionName)
-#         gdbXFile.write('exe("commands")\n')
-        gdbXFile.write('exe("\tprintf \\"SP = %s\\\\n\\", %s")\n' % ("%x", "$sp"))
+        gdbXFile.write("target sim\n")
+        gdbXFile.write("load\n")
+        gdbXFile.write("b %s\n" % func.functionName)
+        gdbXFile.write("commands\n")
+        gdbXFile.write("\tprintf \"SP = %s\\n\", %s\n" % ("%x", "$sp"))
         for varName in listLocalVarNames:
-            gdbXFile.write('exe(\'printf "LocalVar: %s\\\\n"\')\n' % (varName))
-            gdbXFile.write('exe(\'printf "address = 0x%s\\\\n", &%s\')\n' % ("%x", varName))
-            gdbXFile.write('exe(\'ptype %s\')\n' % varName)
-            gdbXFile.write('exe(\'printf "size = %s\\\\n", sizeof(%s)\')\n' % ("%d", varName))
+            gdbXFile.write("\tprintf \"LocalVar: %s\\n\"\n" % (varName))
+            gdbXFile.write("\tprintf \"address = 0x%s\\n\", &%s\n" % ("%x", varName))
+            gdbXFile.write("\tptype %s\n" % varName)
+            gdbXFile.write("\tprintf \"size = %s\\n\", sizeof(%s)\n" % ("%d", varName))
 #         gdbXFile.write("\tcont\n")
-#         gdbXFile.write('exe("end")\n')
-        gdbXFile.write('exe("run")\n')
-        gdbXFile.write('exe("quit")\n')
+        gdbXFile.write("end\n")
+        gdbXFile.write("run\n")
+        gdbXFile.write("quit\n")
         gdbXFile.close()
         
         gdbOFile = open(gdbOFileName, 'w')

power_estimator/Makefile

+# Makefile for cache simulator
+include Makefile.macros
+
+SRC = $(POWEREST_SRC)
+LIB = $(POWEREST_LIB)
+
+INSTALL = cp
+
+all: powerEst
+
+powerEst: 
+	$(MAKE) -C $(SRC)
+	$(INSTALL) $(SRC)/libpowerEst.so $(LIB)
+	
+clean:
+	rm -rf *.o
+	rm -rf $(LIB)/libpowerEst.so

power_estimator/Makefile.macros

+# Configuration for cache simulator
+
+# Stupid Makefile Issue: Make sure no white space at the end of the variable declarations
+
+# http://stackoverflow.com/questions/18136918/how-to-get-current-directory-of-your-makefile
+mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
+current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
+
+# Path to Cache Simulator
+PEST_DIR := $(current_dir)
+
+POWEREST_SRC = $(PEST_DIR)/src
+POWEREST_HEADERS = $(PEST_DIR)/headers/
+POWEREST_LIB = $(PEST_DIR)/lib/

power_estimator/headers/power_estimator.h

@@ -7,7 +7,7 @@
  * period of time, and generates the amount of energy used over the period.
  */
 
-unsigned long long estimate_energy(unsigned long long execCycles,
+extern double estimate_power(unsigned long long execCycles,
 		unsigned long L1_Hits,
 		unsigned long L2_Hits,
 		unsigned long L2_Misses);

power_estimator/src/Makefile

+include ../Makefile.macros
+
+GCC = gcc
+CFLAGS = -O3
+
+HEADERS = $(POWEREST_HEADERS)
+
+CFLAGS += -I$(HEADERS)
+
+# Cache Simulation Source Code
+SOURCES = power_estimator.c $(HEADERS)/power_estimator.h
+OBJECTS = power_estimator.o
+
+all: powerEst
+
+powerEst: $(SOURCES)
+	$(GCC) $(CFLAGS) -c -Wall -Werror -fpic $^
+	$(GCC) -shared -o lib$@.so $(OBJECTS)
+	
+clean:
+	rm -rf *.o libpowerEst.so

power_estimator/src/power_estimator.c

@@ -84,8 +84,8 @@ double estimate_power(char *blockName,
 	totalEnergy += energy;
 	power = energy / ((totalCycles - startCycle) / CPU_freq);
 
-	fprintf(output_fp, "%s, %llu, %f, %llu, %llu, %lu, %lu\n",
-			blockName, startCycles, power, execCycles, memAccessCycles,
+	fprintf(output_fp, "%s, %llu, %f, %llu, %llu, %llu, %llu\n",
+			blockName, startCycle, power, execCycles, memAccessCycles,
 			currBlock_L2_Hits, currBlock_memAccesses);
 
 	return power;
@@ -107,5 +107,5 @@ void power_estimator_init()
 
 void power_estimator_fini()
 {
-	fclose(fp);
+	fclose(output_fp);
 }