Fixed bugs, made ICache Simulation work

Signed-off-by: Gaurav Kukreja <gaurav@gauravk.in>

.gitignore

@@ -10,3 +10,4 @@ examples/crc32/app_dir/in_large.h
 *.pyc
 *.gdbo
 *.gdbx
+*.gch

cache_simulator/Makefile

 # Makefile for cache simulator
 include Makefile.macros
 
-SRC = src
+SRC = $(CACHESIM_SRC)
 LIB = $(CACHESIM_LIB)
 
 INSTALL = cp

cache_simulator/Makefile.macros

 # Configuration for cache simulator
 
+# Stupid Makefile Issue: Make sure no white space at the end of the variable declarations
+
+# http://stackoverflow.com/questions/18136918/how-to-get-current-directory-of-your-makefile
+mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
+current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
+
 # Path to Cache Simulator
-CSIM_DIR = /home/gaurav/workspace/hostCompiledSimulation/cache_simulator
+CSIM_DIR = $(current_dir)
 
 # Hardware Model to use
 CACHESIM_HWMOD = generic
 
+CACHESIM_SRC = $(CSIM_DIR)/src
 CACHESIM_HEADERS = $(CSIM_DIR)/headers/
 CACHESIM_LIB = $(CSIM_DIR)/lib/

cache_simulator/headers/cacheSim.h

@@ -17,7 +17,7 @@
  *
  * @return number of clock cycles spent
  */
-extern unsigned long simICache(unsigned long address, unsigned int nBytes);
+extern unsigned long long simICache(unsigned long address, unsigned int nBytes);
 
 /**
  * Simulates Data Cache access by benchmark
@@ -27,7 +27,7 @@ extern unsigned long simICache(unsigned long address, unsigned int nBytes);
  *
  * @return number of clock cycles spent
  */
-extern unsigned long simDCache(unsigned long address, unsigned int isReadAccess);
+extern unsigned long long simDCache(unsigned long address, unsigned int isReadAccess);
 
 /**
  * Initialize the cache data structures

cache_simulator/src/cacheSim.c

@@ -47,9 +47,9 @@
  *
  * @return number of clock cycles spent
  */
-unsigned long simICache(unsigned long address, unsigned int nBytes)
+unsigned long long simICache(unsigned long address, unsigned int nBytes)
 {
-	unsigned int nCycles;
+	unsigned long long nCycles;
 	cacheSimStat.access_type = ACCESS_TYPE_INVALID;
 	cacheSimStat.nCycles = 0;
 	cacheSimStat.powerMicroJ = 0;
@@ -70,9 +70,9 @@ unsigned long simICache(unsigned long address, unsigned int nBytes)
  *
  * @return number of clock cycles spent
  */
-unsigned long simDCache(unsigned long address, unsigned int isReadAccess)
+unsigned long long simDCache(unsigned long address, unsigned int isReadAccess)
 {
-	unsigned int nCycles;
+	unsigned long long nCycles;
 	cacheSimStat.access_type = ACCESS_TYPE_INVALID;
 	cacheSimStat.nCycles = 0;
 	cacheSimStat.powerMicroJ = 0;

cache_simulator/src/cacheSimHwMod.h

@@ -23,7 +23,7 @@ struct cacheSimHwMod_t
 	 *
 	 * @return number of clock cycles spent
 	 */
-	unsigned long (*simICache) (unsigned long address, unsigned int nBytes);
+	unsigned long long (*simICache) (unsigned long address, unsigned int nBytes);
 
 	/**
 	 * Simulates Data Cache access by benchmark
@@ -33,7 +33,7 @@ struct cacheSimHwMod_t
 	 *
 	 * @return number of clock cycles spent
 	 */
-	unsigned long (*simDCache) (unsigned long address, unsigned int isReadAccess);
+	unsigned long long (*simDCache) (unsigned long address, unsigned int isReadAccess);
 
 	/**
 	 * Initialize the cache data structures

instrument/cacheSimInstrument.py

@@ -97,7 +97,7 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables,
                         addAnnotationToDict(dictAnnotVarFuncDecl,
                                             lineNum,
                                             annot)
-                        annot_str = "extern unsigned long memAccessCycles;"
+                        annot_str = "extern unsigned long long memAccessCycles;"
                         annot = Annotation(annot_str, ISCFileName, lineNum, False)
                         addAnnotationToDict(dictAnnotVarFuncDecl,
                                             lineNum,
@@ -442,7 +442,7 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl
                 line = lc.getline(funcISC.fileName, returnLineNumber)
                 m = re_returnStatement.match(line)
                 if m is not None:
-                    annot_str = 'printf("memAccessCycles = \%lu\\n", memAccessCycles);'
+                    annot_str = 'printf("memAccessCycles = \%llu\\n", memAccessCycles);'
                     annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False)
                     addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot)
                     break

instrument/examples/adpcm/instrumented/Makefile

@@ -12,8 +12,9 @@ all: my_ctop_IR.out
 my_ctop_IR.out: $(APP_SOURCES)
 	$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim
 
+check: my_ctop_IR.out
+	export LD_LIBRARY_PATH=$(CACHESIM_LIB)
+	./my_ctop_IR.out
+
 clean: 
-	rm -rf *.o cacheSimTest 
-	for f in $(SOURCES); do \
-		rm -rf $$f; \
-	done
\ No newline at end of file
+	rm -rf *.o my_ctop_IR.out 

instrument/examples/adpcm/instrumented/adpcm_IR.c

@@ -10,7 +10,7 @@
 #include "ir2c.h"
 #include "cacheSim.h"
 extern unsigned long SP;
-extern unsigned long memAccessCycles;
+extern unsigned long long memAccessCycles;
 
 /***********************************************************
 Copyright 1992 by Stichting Mathematisch Centrum, Amsterdam, The

instrument/examples/adpcm/instrumented/my_ctop_IR.c

@@ -213,7 +213,7 @@ mainbb_12:
 //  # PRED: 7 [39.0%]  (false,exec) 11 [100.0%]  (fallthru,exec)
 // Simulating I Cache for obj block 11
 memAccessCycles += simICache(0x344, 16);
-printf("memAccessCycles = \%lu\n", memAccessCycles);
+printf("memAccessCycles = \%llu\n", memAccessCycles);
   return 0;
 //  # SUCC: EXIT [100.0%] 
 

instrument/examples/sieve/instrumented/erat_sieve_no_print_IR.c

@@ -23,7 +23,7 @@ struct test {
   unsigned int v;
   unsigned int k;
 } m = { 1, 1 };
-
+unsigned long m_addr;
 
 void sieve_func() {
   int j_76;