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hostCompiledSimulation
Commit 7d6da8d1 authored by Gaurav Kukreja's avatar Gaurav Kukreja
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Modifications to instrument for Branch Prediction 

Signed-off-by: Gaurav Kukreja's avatarGaurav Kukreja <gaurav@gauravk.in>
parent 7f60b910
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Showing with 86 additions and 70 deletions
cache_simulator/Makefile.macros
View file @ 7d6da8d1
...@@ -7,7 +7,7 @@ mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST))) ...@@ -7,7 +7,7 @@ mkfile_path := $(abspath $(lastword $(MAKEFILE_LIST)))
current_dir := $(patsubst %/,%,$(dir $(mkfile_path))) current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
# Path to Cache Simulator # Path to Cache Simulator
CSIM_DIR = $(current_dir) CSIM_DIR := $(current_dir)
# Hardware Model to use # Hardware Model to use
CACHESIM_HWMOD = cortexA5 CACHESIM_HWMOD = cortexA5
......
cache_simulator/src/cortexA5HwMod.c
View file @ 7d6da8d1
...@@ -80,7 +80,8 @@ unsigned long L1I_Miss = 0; ...@@ -80,7 +80,8 @@ unsigned long L1I_Miss = 0;
unsigned long L2_Hit_Read = 0; unsigned long L2_Hit_Read = 0;
unsigned long L2_Hit_Writeback = 0; unsigned long L2_Hit_Writeback = 0;
unsigned long L2_Hit_Writethrough = 0; unsigned long L2_Hit_Writethrough = 0;
unsigned long L2_Miss = 0; unsigned long L2I_Miss = 0;
unsigned long L2D_Miss = 0;
/**** LOCAL FUNCTIONS *********************************************************/ /**** LOCAL FUNCTIONS *********************************************************/
...@@ -98,7 +99,7 @@ void initCacheParams () ...@@ -98,7 +99,7 @@ void initCacheParams ()
/*** L1 DCache *****************/ /*** L1 DCache *****************/
L1DCacheConf.lineLenBytes = 32; L1DCacheConf.lineLenBytes = 32;
L1DCacheConf.cacheSizeBytes = 4 * 1024; // 4 KB L1DCacheConf.cacheSizeBytes = 32 * 1024; // 4 KB
L1DCacheConf.numSets = 4; L1DCacheConf.numSets = 4;
L1DCacheConf.numLines = L1DCacheConf.cacheSizeBytes / L1DCacheConf.numLines = L1DCacheConf.cacheSizeBytes /
...@@ -132,7 +133,7 @@ void initCacheParams () ...@@ -132,7 +133,7 @@ void initCacheParams ()
/*** L1 ICache *****************/ /*** L1 ICache *****************/
L1ICacheConf.lineLenBytes = 32; L1ICacheConf.lineLenBytes = 32;
L1ICacheConf.cacheSizeBytes = 4 * 1024; // 4 KB L1ICacheConf.cacheSizeBytes = 32 * 1024; // 4 KB
L1ICacheConf.numSets = 2; L1ICacheConf.numSets = 2;
L1ICacheConf.numLines = L1ICacheConf.cacheSizeBytes / L1ICacheConf.numLines = L1ICacheConf.cacheSizeBytes /
...@@ -166,8 +167,8 @@ void initCacheParams () ...@@ -166,8 +167,8 @@ void initCacheParams ()
/*** L2 Cache *****************/ /*** L2 Cache *****************/
L2CacheConf.lineLenBytes = 32; L2CacheConf.lineLenBytes = 32;
L2CacheConf.cacheSizeBytes = 32 * 1024; // 32 KB L2CacheConf.cacheSizeBytes = 512 * 1024; // 32 KB
L2CacheConf.numSets = 4; L2CacheConf.numSets = 16;
L2CacheConf.numLines = L2CacheConf.cacheSizeBytes / L2CacheConf.numLines = L2CacheConf.cacheSizeBytes /
(L2CacheConf.lineLenBytes * L2CacheConf.numSets); (L2CacheConf.lineLenBytes * L2CacheConf.numSets);
...@@ -194,8 +195,8 @@ void initCacheParams () ...@@ -194,8 +195,8 @@ void initCacheParams ()
L2CacheConf.isWriteThrough = 0; L2CacheConf.isWriteThrough = 0;
L2CacheConf.hitLatency = 14; L2CacheConf.hitLatency = 16;
L2CacheConf.missLatency = 14; L2CacheConf.missLatency = 16;
} }
...@@ -307,7 +308,7 @@ unsigned long long cortexA5_simICache(unsigned long address, ...@@ -307,7 +308,7 @@ unsigned long long cortexA5_simICache(unsigned long address,
} }
// L2 Miss has occured! // L2 Miss has occured!
L2_Miss++; L2I_Miss++;
latency += L2CacheConf.missLatency; latency += L2CacheConf.missLatency;
// Data will be present for next access! // Data will be present for next access!
...@@ -400,7 +401,7 @@ unsigned long long cortexA5_simDCache(unsigned long address, ...@@ -400,7 +401,7 @@ unsigned long long cortexA5_simDCache(unsigned long address,
} }
// L2 Miss has occured! // L2 Miss has occured!
L2_Miss++; L2D_Miss++;
latency += L2CacheConf.missLatency; latency += L2CacheConf.missLatency;
// Data will be present for next access! // Data will be present for next access!
...@@ -447,7 +448,8 @@ void cortexA5_cacheSimFini() ...@@ -447,7 +448,8 @@ void cortexA5_cacheSimFini()
printf("\nL2 Unified Cache\n"); printf("\nL2 Unified Cache\n");
printf("\t Hit Read = %ld\n", L2_Hit_Read); printf("\t Hit Read = %ld\n", L2_Hit_Read);
printf("\t Hit Writeback = %ld\n", L2_Hit_Writeback); printf("\t Hit Writeback = %ld\n", L2_Hit_Writeback);
printf("\t Miss = %ld\n", L2_Miss); printf("\t Inst. Miss = %ld\n", L2I_Miss);
printf("\t Data Miss = %ld\n", L2D_Miss);
free(L1DCache); free(L1DCache);
free(L1ICache); free(L1ICache);
......
examples/Makefile
View file @ 7d6da8d1
...@@ -2,7 +2,7 @@ include ../Makefile.macros ...@@ -2,7 +2,7 @@ include ../Makefile.macros
include Makefile.macros include Makefile.macros
#EXAMPLES = sieve crc32 adpcm sha basicmath #EXAMPLES = sieve crc32 adpcm sha basicmath
EXAMPLES = simple EXAMPLES = adpcm
#EXAMPLES = sha sieve #EXAMPLES = sha sieve
#EXAMPLES = sha #EXAMPLES = sha
STARTADR = 0x10000214 STARTADR = 0x10000214
......
instrument/examples/adpcm/instrumented/Makefile
View file @ 7d6da8d1
include ../../../../cache_simulator/Makefile.macros include ../../../../cache_simulator/Makefile.macros
include ../../../../branch_predictor/Makefile.macros
CC = gcc CC = gcc
CFLAGS = -O2 -std=c99 CFLAGS = -O2 -std=c99
INCLUDE = -I$(CACHESIM_HEADERS) INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS)
LIB = -L$(CACHESIM_LIB) LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB)
APP_SOURCES = my_ctop_IR.c adpcm_IR.c APP_SOURCES = my_ctop_IR.c adpcm_IR.c
all: my_ctop_IR.out all: my_ctop_IR.out
my_ctop_IR.out: $(APP_SOURCES) my_ctop_IR.out: $(APP_SOURCES)
$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim $(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred
check: my_ctop_IR.out check: my_ctop_IR.out
export LD_LIBRARY_PATH=$(CACHESIM_LIB) export LD_LIBRARY_PATH=$(CACHESIM_LIB)
......
instrument/examples/adpcm/instrumented/adpcm_IR.c
View file @ 7d6da8d1
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <stdint.h> #include <stdint.h>
#include "ir2c.h" #include "ir2c.h"
#include "cacheSim.h" #include "cacheSim.h"
#include "branchPred.h"
extern unsigned long SP; extern unsigned long SP;
extern unsigned long long memAccessCycles; extern unsigned long long memAccessCycles;
extern unsigned long long pipelineCycles; extern unsigned long long pipelineCycles;
...@@ -99,7 +100,6 @@ void adpcm_coder (short indata[], unsigned long indata_addr, char outdata[], un ...@@ -99,7 +100,6 @@ void adpcm_coder (short indata[], unsigned long indata_addr, char outdata[], un
uintptr_t ivtmp_28; uintptr_t ivtmp_28;
int bufferstep; int bufferstep;
int outputbuffer; int outputbuffer;
unsigned long outputbuffer_addr = 0x8;
int index; int index;
int vpdiff; int vpdiff;
int valpred; int valpred;
...@@ -108,7 +108,6 @@ void adpcm_coder (short indata[], unsigned long indata_addr, char outdata[], un ...@@ -108,7 +108,6 @@ void adpcm_coder (short indata[], unsigned long indata_addr, char outdata[], un
int delta; int delta;
int sign; int sign;
signed char * outp; signed char * outp;
unsigned long outp_addr = 0x0;
adpcm_coderbb_2: adpcm_coderbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec) // # PRED: ENTRY [100.0%] (fallthru,exec)
...@@ -121,7 +120,7 @@ memAccessCycles += simDCache(0x4a8, 1); // PC Relative Load ...@@ -121,7 +120,7 @@ memAccessCycles += simDCache(0x4a8, 1); // PC Relative Load
memAccessCycles += simICache(0x36c, 44); memAccessCycles += simICache(0x36c, 44);
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247 // TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 249 // TODO: UnmappedLS: Load GlobalVar coder_1_state at line 249
pipelineCycles += 23; pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 7 : 0);
valpred = state->valprev; valpred = state->valprev;
memAccessCycles += simDCache(state_addr, 1); memAccessCycles += simDCache(state_addr, 1);
index = state->index; index = state->index;
...@@ -136,11 +135,11 @@ pipelineCycles += 23; ...@@ -136,11 +135,11 @@ pipelineCycles += 23;
adpcm_coderbb_3: adpcm_coderbb_3:
// # PRED: 2 [91.0%] (true,exec) // # PRED: 2 [91.0%] (true,exec)
memAccessCycles += simDCache((SP + 0x0), 1); // Spilling Register
memAccessCycles += simDCache(0x4a8, 1); // PC Relative Load memAccessCycles += simDCache(0x4a8, 1); // PC Relative Load
memAccessCycles += simDCache((SP + outp_addr), 0);
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x398, 32); memAccessCycles += simICache(0x398, 32);
pipelineCycles += 15; pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
outp = outdata; outp = outdata;
memAccessCycles += simDCache(outdata_addr, 1); memAccessCycles += simDCache(outdata_addr, 1);
ivtmp_28 = 0; ivtmp_28 = 0;
...@@ -150,7 +149,11 @@ pipelineCycles += 15; ...@@ -150,7 +149,11 @@ pipelineCycles += 15;
adpcm_coderbb_4: adpcm_coderbb_4:
// # PRED: 18 [91.0%] (true,exec) 3 [100.0%] (fallthru,exec) // # PRED: 18 [91.0%] (true,exec) 3 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + 0x4), 1); // Reading Spilt Register memAccessCycles += simDCache((SP + 0x4), 1); // Reading Spilt Register
pipelineCycles += 48; memAccessCycles += simDCache((SP + 0x8), 1); // Spilling Register
memAccessCycles += simDCache((SP + 0x8), 1); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x0), 1); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x0), 1); // Spilling Register
pipelineCycles += 48 - (enterBlock(0x106, 0x137) ? 7 : 0);
diff = (int) *(short int *)((uintptr_t)indata + (uintptr_t)ivtmp_28) - valpred; diff = (int) *(short int *)((uintptr_t)indata + (uintptr_t)ivtmp_28) - valpred;
memAccessCycles += simDCache(indata_addr + (sizeof(short ) * (+ivtmp_28)), 1); memAccessCycles += simDCache(indata_addr + (sizeof(short ) * (+ivtmp_28)), 1);
if (diff < 0) if (diff < 0)
...@@ -262,15 +265,12 @@ adpcm_coderbb_15: ...@@ -262,15 +265,12 @@ adpcm_coderbb_15:
adpcm_coderbb_16: adpcm_coderbb_16:
// # PRED: 15 [50.0%] (true,exec) // # PRED: 15 [50.0%] (true,exec)
memAccessCycles += simDCache((SP + outputbuffer_addr), 0);
outputbuffer = delta_37 << 4 & 255; outputbuffer = delta_37 << 4 & 255;
goto adpcm_coderbb_18; goto adpcm_coderbb_18;
// # SUCC: 18 [100.0%] (fallthru,exec) // # SUCC: 18 [100.0%] (fallthru,exec)
adpcm_coderbb_17: adpcm_coderbb_17:
// # PRED: 15 [50.0%] (false,exec) // # PRED: 15 [50.0%] (false,exec)
memAccessCycles += simDCache((SP + outputbuffer_addr), 1);
memAccessCycles += simDCache((SP + outp_addr), 0);
*outp = (signed char) delta_37 & 15 | (signed char) outputbuffer; *outp = (signed char) delta_37 & 15 | (signed char) outputbuffer;
outp = (uintptr_t)outp + 1; outp = (uintptr_t)outp + 1;
// # SUCC: 18 [100.0%] (fallthru,exec) // # SUCC: 18 [100.0%] (fallthru,exec)
...@@ -279,9 +279,8 @@ adpcm_coderbb_18: ...@@ -279,9 +279,8 @@ adpcm_coderbb_18:
// # PRED: 16 [100.0%] (fallthru,exec) 17 [100.0%] (fallthru,exec) // # PRED: 16 [100.0%] (fallthru,exec) 17 [100.0%] (fallthru,exec)
// Simulating I Cache for obj block 2 // Simulating I Cache for obj block 2
memAccessCycles += simICache(0x3b8, 200); memAccessCycles += simICache(0x3b8, 200);
// TODO: UnmappedLS: Store GlobalVar adpcmdata at line 306
// TODO: UnmappedLS: Load GlobalVar pcmdata at line 263 // TODO: UnmappedLS: Load GlobalVar pcmdata at line 263
// TODO: UnmappedLS: Load LocalVar outp at line 305
// TODO: UnmappedLS: Store GlobalVar pcmdata at line 306
bufferstep = bufferstep == 0; bufferstep = bufferstep == 0;
len = len + -1; len = len + -1;
ivtmp_28 = ivtmp_28 + 2; ivtmp_28 = ivtmp_28 + 2;
...@@ -293,7 +292,9 @@ memAccessCycles += simICache(0x3b8, 200); ...@@ -293,7 +292,9 @@ memAccessCycles += simICache(0x3b8, 200);
adpcm_coderbb_19: adpcm_coderbb_19:
// # PRED: 18 [9.0%] (false,exec) // # PRED: 18 [9.0%] (false,exec)
pipelineCycles += 10; memAccessCycles += simDCache((SP + 0x8), 1); // Reading Spilt Register
memAccessCycles += simDCache((SP + 0x0), 1); // Reading Spilt Register
pipelineCycles += 10 - (enterBlock(0x138, 0x13b) ? 7 : 0);
if (bufferstep == 0) if (bufferstep == 0)
goto adpcm_coderbb_20; goto adpcm_coderbb_20;
else else
...@@ -302,7 +303,6 @@ pipelineCycles += 10; ...@@ -302,7 +303,6 @@ pipelineCycles += 10;
adpcm_coderbb_20: adpcm_coderbb_20:
// # PRED: 19 [67.0%] (true,exec) // # PRED: 19 [67.0%] (true,exec)
memAccessCycles += simDCache((SP + outputbuffer_addr), 1);
*outp = (signed char) (signed char) outputbuffer; *outp = (signed char) (signed char) outputbuffer;
// # SUCC: 21 [100.0%] (fallthru,exec) // # SUCC: 21 [100.0%] (fallthru,exec)
...@@ -310,14 +310,13 @@ adpcm_coderbb_21: ...@@ -310,14 +310,13 @@ adpcm_coderbb_21:
// # PRED: 19 [33.0%] (false,exec) 20 [100.0%] (fallthru,exec) 2 [9.0%] (false,exec) // # PRED: 19 [33.0%] (false,exec) 20 [100.0%] (fallthru,exec) 2 [9.0%] (false,exec)
// Simulating I Cache for obj block 3 // Simulating I Cache for obj block 3
memAccessCycles += simICache(0x480, 16); memAccessCycles += simICache(0x480, 16);
// TODO: UnmappedLS: Load LocalVar outp at line 314 // TODO: UnmappedLS: Store GlobalVar adpcmdata at line 315
// TODO: UnmappedLS: Store GlobalVar stepsizeTable at line 315
memAccessCycles += simDCache((SP + 0xc), 1); // Reading Spilt Register memAccessCycles += simDCache((SP + 0xc), 1); // Reading Spilt Register
// Simulating I Cache for obj block 4 // Simulating I Cache for obj block 4
memAccessCycles += simICache(0x490, 24); memAccessCycles += simICache(0x490, 24);
// TODO: UnmappedLS: Store GlobalVar coder_1_state at line 317 // TODO: UnmappedLS: Store GlobalVar coder_1_state at line 317
// TODO: UnmappedLS: Store GlobalVar coder_1_state at line 318 // TODO: UnmappedLS: Store GlobalVar coder_1_state at line 318
pipelineCycles += 19; pipelineCycles += 19 - (enterBlock(0x13c, 0x141) ? 7 : 0);
state->valprev = (short int) (short int) valpred; state->valprev = (short int) (short int) valpred;
memAccessCycles += simDCache(state_addr, 0); memAccessCycles += simDCache(state_addr, 0);
state->index = (char) (char) index; state->index = (char) (char) index;
......
instrument/examples/adpcm/instrumented/my_ctop_IR.c
View file @ 7d6da8d1
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <stdint.h> #include <stdint.h>
#include "ir2c.h" #include "ir2c.h"
#include "cacheSim.h" #include "cacheSim.h"
#include "branchPred.h"
unsigned long SP = 0x1234; unsigned long SP = 0x1234;
unsigned long long memAccessCycles = 0; unsigned long long memAccessCycles = 0;
unsigned long long pipelineCycles = 0; unsigned long long pipelineCycles = 0;
...@@ -63,6 +64,7 @@ int main() { ...@@ -63,6 +64,7 @@ int main() {
mainbb_2: mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec) // # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(); cacheSimInit();
branchPred_init();
SP = SP + 0x30; SP = SP + 0x30;
memAccessCycles += simDCache(0x354, 1); // PC Relative Load memAccessCycles += simDCache(0x354, 1); // PC Relative Load
memAccessCycles += simDCache(0x358, 1); // PC Relative Load memAccessCycles += simDCache(0x358, 1); // PC Relative Load
...@@ -70,7 +72,7 @@ memAccessCycles += simDCache(ARR_SIZE_addr, 1); ...@@ -70,7 +72,7 @@ memAccessCycles += simDCache(ARR_SIZE_addr, 1);
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0); memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0);
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 36); memAccessCycles += simICache(0x200, 36);
pipelineCycles += 27; pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 7 : 0);
ARR_SIZE_0 = ARR_SIZE; ARR_SIZE_0 = ARR_SIZE;
j = ARR_SIZE_0 / 10240; j = ARR_SIZE_0 / 10240;
if (j != 0) if (j != 0)
...@@ -88,14 +90,14 @@ memAccessCycles += simDCache(0x364, 1); // PC Relative Load ...@@ -88,14 +90,14 @@ memAccessCycles += simDCache(0x364, 1); // PC Relative Load
memAccessCycles += simDCache(0x368, 1); // PC Relative Load memAccessCycles += simDCache(0x368, 1); // PC Relative Load
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x224, 40); memAccessCycles += simICache(0x224, 40);
pipelineCycles += 21; pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 7 : 0);
end_43 = 0; end_43 = 0;
count = 0; count = 0;
// # SUCC: 3 [100.0%] (fallthru) // # SUCC: 3 [100.0%] (fallthru)
mainbb_3: mainbb_3:
// # PRED: 13 [100.0%] (fallthru) 14 [100.0%] (fallthru) // # PRED: 13 [100.0%] (fallthru) 14 [100.0%] (fallthru)
pipelineCycles += 9; pipelineCycles += 9 - (enterBlock(0xa9, 0xab) ? 7 : 0);
end_46 = end_43 + 10240; end_46 = end_43 + 10240;
if (end_43 < end_46) if (end_43 < end_46)
goto mainbb_4; goto mainbb_4;
...@@ -108,7 +110,7 @@ mainbb_4: ...@@ -108,7 +110,7 @@ mainbb_4:
memAccessCycles += simDCache((SP + 0x4), 1); // Reading Spilt Register memAccessCycles += simDCache((SP + 0x4), 1); // Reading Spilt Register
// Simulating I Cache for obj block 3 // Simulating I Cache for obj block 3
memAccessCycles += simICache(0x258, 20); memAccessCycles += simICache(0x258, 20);
pipelineCycles += 13; pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
i_45 = (int) end_43; i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45]; ivtmp_34 = (uintptr_t)&in_Data[i_45];
end_44 = end_43; end_44 = end_43;
...@@ -120,7 +122,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0); ...@@ -120,7 +122,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0);
// Simulating I Cache for obj block 4 // Simulating I Cache for obj block 4
memAccessCycles += simICache(0x26c, 36); memAccessCycles += simICache(0x26c, 36);
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179 // TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16; pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34); pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
i_45 = i_45 + 1; i_45 = i_45 + 1;
end_44 = (long unsigned int) i_45; end_44 = (long unsigned int) i_45;
...@@ -135,7 +137,7 @@ mainbb_6: ...@@ -135,7 +137,7 @@ mainbb_6:
// # PRED: 5 [1.0%] (false,exec) 3 [1.0%] (false,exec) // # PRED: 5 [1.0%] (false,exec) 3 [1.0%] (false,exec)
// Simulating I Cache for obj block 5 // Simulating I Cache for obj block 5
memAccessCycles += simICache(0x290, 40); memAccessCycles += simICache(0x290, 40);
pipelineCycles += 14; pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr); adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr);
count = count + 1; count = count + 1;
if (j > count) if (j > count)
...@@ -158,7 +160,7 @@ memAccessCycles += simDCache(0x358, 1); // PC Relative Load ...@@ -158,7 +160,7 @@ memAccessCycles += simDCache(0x358, 1); // PC Relative Load
memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1); memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1);
// Simulating I Cache for obj block 6 // Simulating I Cache for obj block 6
memAccessCycles += simICache(0x2b8, 32); memAccessCycles += simICache(0x2b8, 32);
pipelineCycles += 19; pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 7 : 0);
if (ARR_SIZE_0 % 10240 != 0) if (ARR_SIZE_0 % 10240 != 0)
goto mainbb_8; goto mainbb_8;
else else
...@@ -170,7 +172,7 @@ mainbb_8: ...@@ -170,7 +172,7 @@ mainbb_8:
memAccessCycles += simDCache(0x354, 1); // PC Relative Load memAccessCycles += simDCache(0x354, 1); // PC Relative Load
// Simulating I Cache for obj block 7 // Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2d8, 24); memAccessCycles += simICache(0x2d8, 24);
pipelineCycles += 14; pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
start_40 = j * 10240; start_40 = j * 10240;
memAccessCycles += simDCache(ARR_SIZE_addr, 1); memAccessCycles += simDCache(ARR_SIZE_addr, 1);
end = ARR_SIZE; end = ARR_SIZE;
...@@ -186,7 +188,7 @@ memAccessCycles += simDCache(0x35c, 1); // PC Relative Load ...@@ -186,7 +188,7 @@ memAccessCycles += simDCache(0x35c, 1); // PC Relative Load
memAccessCycles += simDCache(0x360, 1); // PC Relative Load memAccessCycles += simDCache(0x360, 1); // PC Relative Load
// Simulating I Cache for obj block 8 // Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2f0, 28); memAccessCycles += simICache(0x2f0, 28);
pipelineCycles += 13; pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
i = (int) start_40; i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i]; ivtmp_28 = (uintptr_t)&in_Data[i];
D_2229 = (int) end; D_2229 = (int) end;
...@@ -199,7 +201,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0); ...@@ -199,7 +201,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0);
// Simulating I Cache for obj block 9 // Simulating I Cache for obj block 9
memAccessCycles += simICache(0x30c, 36); memAccessCycles += simICache(0x30c, 36);
// TODO: UnmappedLS: Inaccurately Matched Load at line 219 // TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16; pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28); pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
i = i + 1; i = i + 1;
start = (long unsigned int) i; start = (long unsigned int) i;
...@@ -217,7 +219,7 @@ memAccessCycles += simDCache(0x364, 1); // PC Relative Load ...@@ -217,7 +219,7 @@ memAccessCycles += simDCache(0x364, 1); // PC Relative Load
memAccessCycles += simDCache(0x368, 1); // PC Relative Load memAccessCycles += simDCache(0x368, 1); // PC Relative Load
// Simulating I Cache for obj block 10 // Simulating I Cache for obj block 10
memAccessCycles += simICache(0x330, 20); memAccessCycles += simICache(0x330, 20);
pipelineCycles += 11; pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 7 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr); adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr);
// # SUCC: 12 [100.0%] (fallthru,exec) // # SUCC: 12 [100.0%] (fallthru,exec)
...@@ -228,7 +230,7 @@ memAccessCycles += simICache(0x344, 16); ...@@ -228,7 +230,7 @@ memAccessCycles += simICache(0x344, 16);
printf("memAccessCycles = \%llu\n", memAccessCycles); printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles); printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini(); cacheSimFini();
pipelineCycles += 18; pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 7 : 0);
return 0; return 0;
// # SUCC: EXIT [100.0%] // # SUCC: EXIT [100.0%]
......
instrument/examples/sieve/instrumented/Makefile
View file @ 7d6da8d1
include ../../../../cache_simulator/Makefile.macros include ../../../../cache_simulator/Makefile.macros
include ../../../../branch_predictor/Makefile.macros
CC = gcc CC = gcc
CFLAGS = -O2 -std=c99 CFLAGS = -O2 -std=c99
INCLUDE = -I$(CACHESIM_HEADERS) INCLUDE = -I$(CACHESIM_HEADERS) -I$(BPRED_HEADERS)
LIB = -L$(CACHESIM_LIB) LIB = -L$(CACHESIM_LIB) -L$(BPRED_LIB)
APP_SOURCES = erat_sieve_no_print_IR.c APP_SOURCES = erat_sieve_no_print_IR.c
all: sieve.out all: sieve.out
sieve.out: $(APP_SOURCES) sieve.out: $(APP_SOURCES)
$(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim $(CC) $(CFLAGS) $(INCLUDE) $(LIB) -o $@ $^ -lcacheSim -lbranchPred
clean: clean:
rm -rf *.o cacheSimTest rm -rf *.o cacheSimTest
......
instrument/examples/sieve/instrumented/erat_sieve_no_print_IR.c
View file @ 7d6da8d1
...@@ -9,6 +9,7 @@ ...@@ -9,6 +9,7 @@
#include <stdint.h> #include <stdint.h>
#include "ir2c.h" #include "ir2c.h"
#include "cacheSim.h" #include "cacheSim.h"
#include "branchPred.h"
unsigned long SP = 0x1234; unsigned long SP = 0x1234;
unsigned long long memAccessCycles = 0; unsigned long long memAccessCycles = 0;
unsigned long long pipelineCycles = 0; unsigned long long pipelineCycles = 0;
...@@ -49,7 +50,7 @@ SP = SP + 0x1e84a0; ...@@ -49,7 +50,7 @@ SP = SP + 0x1e84a0;
memAccessCycles += simDCache(0x35c, 1); // PC Relative Load memAccessCycles += simDCache(0x35c, 1); // PC Relative Load
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 40); memAccessCycles += simICache(0x200, 40);
pipelineCycles += 24; pipelineCycles += 24 - (enterBlock(0x96, 0x9f) ? 7 : 0);
ivtmp_68 = 0; ivtmp_68 = 0;
// # SUCC: 3 [100.0%] (fallthru,exec) // # SUCC: 3 [100.0%] (fallthru,exec)
...@@ -58,7 +59,7 @@ sieve_funcbb_3: ...@@ -58,7 +59,7 @@ sieve_funcbb_3:
memAccessCycles += simDCache(results_addr + (4 * (+ivtmp_68)), 0); memAccessCycles += simDCache(results_addr + (4 * (+ivtmp_68)), 0);
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x228, 28); memAccessCycles += simICache(0x228, 28);
pipelineCycles += 13; pipelineCycles += 13 - (enterBlock(0xa0, 0xa6) ? 7 : 0);
*(unsigned int*)((uintptr_t)&results + (uintptr_t)ivtmp_68) = 0; *(unsigned int*)((uintptr_t)&results + (uintptr_t)ivtmp_68) = 0;
memAccessCycles += simDCache((SP + sieve_addr + (4 * (+ivtmp_68))), 0); memAccessCycles += simDCache((SP + sieve_addr + (4 * (+ivtmp_68))), 0);
*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)ivtmp_68) = 1; *(unsigned int*)((uintptr_t)&sieve + (uintptr_t)ivtmp_68) = 1;
...@@ -73,7 +74,7 @@ sieve_funcbb_17: ...@@ -73,7 +74,7 @@ sieve_funcbb_17:
// # PRED: 3 [1.0%] (false,exec) // # PRED: 3 [1.0%] (false,exec)
// Simulating I Cache for obj block 2 // Simulating I Cache for obj block 2
memAccessCycles += simICache(0x244, 52); memAccessCycles += simICache(0x244, 52);
pipelineCycles += 21; pipelineCycles += 21 - (enterBlock(0xa7, 0xb3) ? 7 : 0);
ivtmp_49 = 6; ivtmp_49 = 6;
ivtmp_58 = 4; ivtmp_58 = 4;
i_72 = 2; i_72 = 2;
...@@ -83,7 +84,7 @@ sieve_funcbb_4: ...@@ -83,7 +84,7 @@ sieve_funcbb_4:
// # PRED: 7 [99.0%] (true,exec) 17 [100.0%] (fallthru) // # PRED: 7 [99.0%] (true,exec) 17 [100.0%] (fallthru)
// Simulating I Cache for obj block 3 // Simulating I Cache for obj block 3
memAccessCycles += simICache(0x278, 16); memAccessCycles += simICache(0x278, 16);
pipelineCycles += 9; pipelineCycles += 9 - (enterBlock(0xb4, 0xb7) ? 7 : 0);
D_2263 = (unsigned int) i_72; D_2263 = (unsigned int) i_72;
memAccessCycles += simDCache((SP + sieve_addr + (4 * (+D_2263*4))), 1); memAccessCycles += simDCache((SP + sieve_addr + (4 * (+D_2263*4))), 1);
if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2263 * 4) != 0) if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2263 * 4) != 0)
...@@ -96,7 +97,7 @@ sieve_funcbb_5: ...@@ -96,7 +97,7 @@ sieve_funcbb_5:
// # PRED: 4 [50.0%] (true,exec) // # PRED: 4 [50.0%] (true,exec)
// Simulating I Cache for obj block 4 // Simulating I Cache for obj block 4
memAccessCycles += simICache(0x288, 12); memAccessCycles += simICache(0x288, 12);
pipelineCycles += 8; pipelineCycles += 8 - (enterBlock(0xb8, 0xba) ? 7 : 0);
j_76 = (int) ivtmp_58; j_76 = (int) ivtmp_58;
if (j_76 <= 499999) if (j_76 <= 499999)
goto sieve_funcbb_18; goto sieve_funcbb_18;
...@@ -108,7 +109,7 @@ sieve_funcbb_18: ...@@ -108,7 +109,7 @@ sieve_funcbb_18:
// # PRED: 5 [91.0%] (true,exec) // # PRED: 5 [91.0%] (true,exec)
// Simulating I Cache for obj block 5 // Simulating I Cache for obj block 5
memAccessCycles += simICache(0x294, 4); memAccessCycles += simICache(0x294, 4);
pipelineCycles += 8; pipelineCycles += 8 - (enterBlock(0xbb, 0xbb) ? 7 : 0);
ivtmp_74 = ivtmp_49; ivtmp_74 = ivtmp_49;
// # SUCC: 6 [100.0%] (fallthru) // # SUCC: 6 [100.0%] (fallthru)
...@@ -117,7 +118,7 @@ sieve_funcbb_6: ...@@ -117,7 +118,7 @@ sieve_funcbb_6:
memAccessCycles += simDCache((SP + sieve_addr + (4 * (j_76))), 0); memAccessCycles += simDCache((SP + sieve_addr + (4 * (j_76))), 0);
// Simulating I Cache for obj block 6 // Simulating I Cache for obj block 6
memAccessCycles += simICache(0x298, 40); memAccessCycles += simICache(0x298, 40);
pipelineCycles += 17; pipelineCycles += 17 - (enterBlock(0xbc, 0xc5) ? 7 : 0);
sieve[j_76] = 0; sieve[j_76] = 0;
D_2252 = (unsigned int) j_76 + D_2263; D_2252 = (unsigned int) j_76 + D_2263;
j_76 = (int) D_2252; j_76 = (int) D_2252;
...@@ -132,7 +133,7 @@ sieve_funcbb_7: ...@@ -132,7 +133,7 @@ sieve_funcbb_7:
// # PRED: 4 [50.0%] (false,exec) 6 [9.0%] (false,exec) 5 [9.0%] (false,exec) // # PRED: 4 [50.0%] (false,exec) 6 [9.0%] (false,exec) 5 [9.0%] (false,exec)
// Simulating I Cache for obj block 7 // Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2c0, 24); memAccessCycles += simICache(0x2c0, 24);
pipelineCycles += 19; pipelineCycles += 19 - (enterBlock(0xc6, 0xcb) ? 7 : 0);
i_72 = i_72 + 1; i_72 = i_72 + 1;
ivtmp_58 = ivtmp_58 + 2; ivtmp_58 = ivtmp_58 + 2;
ivtmp_49 = ivtmp_49 + 3; ivtmp_49 = ivtmp_49 + 3;
...@@ -147,14 +148,14 @@ sieve_funcbb_8: ...@@ -147,14 +148,14 @@ sieve_funcbb_8:
memAccessCycles += simDCache(0x35c, 1); // PC Relative Load memAccessCycles += simDCache(0x35c, 1); // PC Relative Load
// Simulating I Cache for obj block 8 // Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2d8, 24); memAccessCycles += simICache(0x2d8, 24);
pipelineCycles += 13; pipelineCycles += 13 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
j = 2; j = 2;
i = 0; i = 0;
// # SUCC: 9 [100.0%] (fallthru,exec) // # SUCC: 9 [100.0%] (fallthru,exec)
sieve_funcbb_9: sieve_funcbb_9:
// # PRED: 11 [99.0%] (true,exec) 8 [100.0%] (fallthru,exec) // # PRED: 11 [99.0%] (true,exec) 8 [100.0%] (fallthru,exec)
pipelineCycles += 12; pipelineCycles += 12 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
D_2240 = (unsigned int) j; D_2240 = (unsigned int) j;
memAccessCycles += simDCache((SP + sieve_addr + (4 * (+D_2240*4))), 1); memAccessCycles += simDCache((SP + sieve_addr + (4 * (+D_2240*4))), 1);
if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2240 * 4) != 0) if (*(unsigned int*)((uintptr_t)&sieve + (uintptr_t)D_2240 * 4) != 0)
...@@ -187,7 +188,7 @@ memAccessCycles += simDCache(0x35c, 1); // PC Relative Load ...@@ -187,7 +188,7 @@ memAccessCycles += simDCache(0x35c, 1); // PC Relative Load
memAccessCycles += simDCache(results_addr + (4 * (0)), 1); memAccessCycles += simDCache(results_addr + (4 * (0)), 1);
// Simulating I Cache for obj block 10 // Simulating I Cache for obj block 10
memAccessCycles += simICache(0x30c, 16); memAccessCycles += simICache(0x30c, 16);
pipelineCycles += 9; pipelineCycles += 9 - (enterBlock(0xd9, 0xdc) ? 7 : 0);
if (results[0] == 0) if (results[0] == 0)
goto sieve_funcbb_16; goto sieve_funcbb_16;
else else
...@@ -198,7 +199,7 @@ sieve_funcbb_13: ...@@ -198,7 +199,7 @@ sieve_funcbb_13:
// # PRED: 12 [95.5%] (false,exec) // # PRED: 12 [95.5%] (false,exec)
// Simulating I Cache for obj block 11 // Simulating I Cache for obj block 11
memAccessCycles += simICache(0x31c, 12); memAccessCycles += simICache(0x31c, 12);
pipelineCycles += 10; pipelineCycles += 10 - (enterBlock(0xdd, 0xdf) ? 7 : 0);
ivtmp_36 = (uintptr_t)&results; ivtmp_36 = (uintptr_t)&results;
D_2230 = ivtmp_36 + 1999996; D_2230 = ivtmp_36 + 1999996;
// # SUCC: 14 [100.0%] (fallthru,exec) // # SUCC: 14 [100.0%] (fallthru,exec)
...@@ -208,7 +209,7 @@ sieve_funcbb_14: ...@@ -208,7 +209,7 @@ sieve_funcbb_14:
// Simulating I Cache for obj block 12 // Simulating I Cache for obj block 12
memAccessCycles += simICache(0x328, 12); memAccessCycles += simICache(0x328, 12);
// TODO: UnmappedLS: Load GlobalVar results at line 224 // TODO: UnmappedLS: Load GlobalVar results at line 224
pipelineCycles += 8; pipelineCycles += 8 - (enterBlock(0xe0, 0xe2) ? 7 : 0);
if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0) if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0)
goto sieve_funcbb_16; goto sieve_funcbb_16;
else else
...@@ -219,7 +220,7 @@ sieve_funcbb_15: ...@@ -219,7 +220,7 @@ sieve_funcbb_15:
// # PRED: 14 [95.5%] (false,exec) // # PRED: 14 [95.5%] (false,exec)
// Simulating I Cache for obj block 13 // Simulating I Cache for obj block 13
memAccessCycles += simICache(0x334, 12); memAccessCycles += simICache(0x334, 12);
pipelineCycles += 9; pipelineCycles += 9 - (enterBlock(0xe3, 0xe5) ? 7 : 0);
ivtmp_36 = ivtmp_36 + 4; ivtmp_36 = ivtmp_36 + 4;
if (ivtmp_36 != D_2230) if (ivtmp_36 != D_2230)
goto sieve_funcbb_14; goto sieve_funcbb_14;
...@@ -233,7 +234,7 @@ memAccessCycles += simDCache(0x360, 1); // PC Relative Load ...@@ -233,7 +234,7 @@ memAccessCycles += simDCache(0x360, 1); // PC Relative Load
memAccessCycles += simDCache(m_addr, 0); memAccessCycles += simDCache(m_addr, 0);
// Simulating I Cache for obj block 14 // Simulating I Cache for obj block 14
memAccessCycles += simICache(0x340, 28); memAccessCycles += simICache(0x340, 28);
pipelineCycles += 20; pipelineCycles += 20 - (enterBlock(0xe6, 0xec) ? 7 : 0);
m.v = 0; m.v = 0;
return; return;
// # SUCC: EXIT [100.0%] // # SUCC: EXIT [100.0%]
...@@ -246,10 +247,11 @@ int main (void) { ...@@ -246,10 +247,11 @@ int main (void) {
mainbb_2: mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec) // # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(); cacheSimInit();
branchPred_init();
SP = SP + 0x8; SP = SP + 0x8;
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x364, 20); memAccessCycles += simICache(0x364, 20);
pipelineCycles += 12; pipelineCycles += 12 - (enterBlock(0xf1, 0xf5) ? 7 : 0);
sieve_func (); sieve_func ();
printf("memAccessCycles = \%llu\n", memAccessCycles); printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles); printf("pipelineCycles = \%llu\n", pipelineCycles);
......
instrument/instrument.py
View file @ 7d6da8d1
...@@ -56,6 +56,11 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables, ...@@ -56,6 +56,11 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables,
if line.startswith('#include "ir2c.h"'): if line.startswith('#include "ir2c.h"'):
annot_str = '#include "cacheSim.h"' annot_str = '#include "cacheSim.h"'
annot = Annotation(annot_str, ISCFileName, lineNum, False) annot = Annotation(annot_str, ISCFileName, lineNum, False)
addAnnotationToDict(dictAnnotVarFuncDecl,
lineNum,
annot)
annot_str = '#include "branchPred.h"'
annot = Annotation(annot_str, ISCFileName, lineNum, False)
addAnnotationToDict(dictAnnotVarFuncDecl, addAnnotationToDict(dictAnnotVarFuncDecl,
lineNum, lineNum,
annot) annot)
...@@ -310,6 +315,9 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl ...@@ -310,6 +315,9 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl
annot_str = "cacheSimInit();" annot_str = "cacheSimInit();"
annot = Annotation(annot_str, funcISC.fileName, funcISC.cfg.listBlocks[0].startLine-1, False) annot = Annotation(annot_str, funcISC.fileName, funcISC.cfg.listBlocks[0].startLine-1, False)
addAnnotationToDict(dictAnnotLoadStore, funcISC.cfg.listBlocks[0].startLine-1, annot) addAnnotationToDict(dictAnnotLoadStore, funcISC.cfg.listBlocks[0].startLine-1, annot)
annot_str = "branchPred_init();"
annot = Annotation(annot_str, funcISC.fileName, funcISC.cfg.listBlocks[0].startLine-1, False)
addAnnotationToDict(dictAnnotLoadStore, funcISC.cfg.listBlocks[0].startLine-1, annot)
funcObj = find(lambda fn: fn.functionName == funcISC.functionName, listObjdumpFunctions) funcObj = find(lambda fn: fn.functionName == funcISC.functionName, listObjdumpFunctions)
annot_str = "SP = SP + 0x%x;" % (funcObj.stackSize) annot_str = "SP = SP + 0x%x;" % (funcObj.stackSize)
......
instrument/match_cfg.py
View file @ 7d6da8d1
...@@ -581,12 +581,11 @@ def match_cfg(listISCFileNames, listObjdumpFileNames, listBinaryFileNames): ...@@ -581,12 +581,11 @@ def match_cfg(listISCFileNames, listObjdumpFileNames, listBinaryFileNames):
printDebugMapCFG(listISCFunctions, listObjdumpFunctions, gdbMapping) printDebugMapCFG(listISCFunctions, listObjdumpFunctions, gdbMapping)
# for funcISC in listISCFunctions: for funcISC in listISCFunctions:
# funcObj = find(lambda fn: fn.functionName == funcISC.functionName, listObjdumpFunctions) funcObj = find(lambda fn: fn.functionName == funcISC.functionName, listObjdumpFunctions)
# # display_cfgs(app, funcISC.cfg, funcObj.cfg, "%s" % funcISC.functionName) psISCFileName = draw_cfg(funcISC, outputPath)
# psISCFileName = draw_cfg(funcISC, outputPath) psObjFileName = draw_cfg(funcObj, outputPath)
# psObjFileName = draw_cfg(funcObj, outputPath) call(args = ["evince", psISCFileName, psObjFileName])
# call(args = ["evince", psISCFileName, psObjFileName])
return listISCFunctions, listObjdumpFunctions return listISCFunctions, listObjdumpFunctions
......
instrument/pipeline_sim.py
View file @ 7d6da8d1
...@@ -412,7 +412,9 @@ def annot_pipeline_sim(listISCFunctions, ...@@ -412,7 +412,9 @@ def annot_pipeline_sim(listISCFunctions,
# Block Done! # Block Done!
blockIndISC = blockObj.mapsTo[0] blockIndISC = blockObj.mapsTo[0]
blockISC = funcISC.cfg.listBlocks[blockIndISC] blockISC = funcISC.cfg.listBlocks[blockIndISC]
annot_str = "pipelineCycles += %d;" % (currBlockCycles) annot_str = "pipelineCycles += %d - (enterBlock(0x%x, 0x%x) ? 7 : 0);" % (currBlockCycles,
blockObj.startLine,
blockObj.endLine)
annot = Annotation(annot_str, annot = Annotation(annot_str,
funcISC.fileName, funcISC.fileName,
blockISC.startLine, blockISC.startLine,
......
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