Combined commit for 2 major changes

 * Added pipeline_sim for simulating pipeline, not completely tested
 * Added Cache HW Mod for Cortex A5.
Signed-off-by: Gaurav Kukreja <gaurav@gauravk.in>

cache_simulator/Makefile.macros

@@ -10,7 +10,7 @@ current_dir := $(patsubst %/,%,$(dir $(mkfile_path)))
 CSIM_DIR = $(current_dir)
 
 # Hardware Model to use
-CACHESIM_HWMOD = generic
+CACHESIM_HWMOD = cortexA5
 
 CACHESIM_SRC = $(CSIM_DIR)/src
 CACHESIM_HEADERS = $(CSIM_DIR)/headers/

cache_simulator/src/Makefile

@@ -15,6 +15,11 @@ ifeq ($(CACHESIM_HWMOD),generic)
     OBJECTS += genericHwMod.o
 endif
 
+ifeq ($(CACHESIM_HWMOD),cortexA5)
+    SOURCES += cortexA5HwMod.c
+    OBJECTS += cortexA5HwMod.o
+endif
+
 all: cacheSim
 
 cacheSim: $(SOURCES)

instrument/annotation.py

+import logging
+
+class Annotation:
+    def __init__(self, annotation, fileName, lineNum, replace = False):
+        self.fileName = fileName
+        self.lineNum = lineNum
+        self.annotation = annotation
+        self.replace = replace
+        
+    def debug(self):
+        logging.debug("%s:%d: %s" % (self.fileName, self.lineNum, self.annotation))
+        
+def debugDictAnnot(dictAnnot):
+    for lineNum in dictAnnot.iterkeys():
+        for annot in dictAnnot[lineNum]:
+            annot.debug()
+
+def addAnnotationToDict(dict, lineNum, annot):
+    if lineNum not in dict:
+        print("adding annotation on line %d" % lineNum)
+        dict[lineNum] = [annot]
+    else:
+        for a in dict[lineNum]:
+            if a.annotation == annot.annotation and a.fileName == annot.fileName:
+                return
+        dict[lineNum].append(annot)
\ No newline at end of file

instrument/arm_isa_regex.py

@@ -14,7 +14,7 @@ re_mvnInst = re.compile("\s*(?:mvn)s?(?:%s)?\s*(?P<destReg>%s),\s*(?:%s)(?:%s)"
                         (Cond, Reg, Operand2, EndLine))
 
 ArithOpcode = "(?P<arithOpcode>add|adc|sub|sbc|rsb|rsc|mul|mla)s?" # There are more that I have ignored for now
-re_arithInst = re.compile("\s*(?:%s)(?:%s)?\s*(?P<destReg>%s),\s*(?P<op1Reg>%s),\s*(?:%s)(?:%s)" % 
+re_arithInst = re.compile("\s*(?:%s)(?:%s)?\s*(?P<destReg>%s),\s*(?P<op1Reg>%s),\s*(?P<op2>%s)(?:%s)" % 
                           (ArithOpcode, Cond, Reg, Reg, Operand2, EndLine))
 
 ArithLongOpcode = "(?P<arithLongOpcode>umull|umlal|smull|smlal)"
@@ -25,7 +25,7 @@ LogicOpcode = "(?P<logicOpcode>and|eor|orr|bic)s?"
 re_logicInst = re.compile("\s*(?:%s)(?:%s)?\s*(?P<destReg>%s),\s*(?P<op1Reg>%s),\s*(?:%s)(?:%s)" % 
                           (LogicOpcode, Cond, Reg, Reg, Operand2, EndLine))
 
-re_shiftInst = re.compile("\s*(?:%s)(?:%s)?\s*(?P<destReg>%s),\s*(?P<op1Reg>%s),\s*#(?P<op2ImedVal>\d*)(?:%s)" %
+re_shiftInst = re.compile("\s*(?P<shiftOpcode>%s)(?:%s)?\s*(?P<destReg>%s),\s*(?P<op1Reg>%s),\s*#(?P<op2ImedVal>\d*)(?:%s)" %
                           (ShiftOpcode, Cond, Reg, Reg, EndLine))
 
 BranchOpcode = "(?P<branchOpcode>b|bl|bx|blx|bxj)"
@@ -41,8 +41,8 @@ AMode2_2 = "\[(?P<am2_2BaseReg>%s),\s*#(?P<am2_2ImedOff>-?\d*)\]" % (Reg)
 AMode2_3 = "\[(?P<am2_3BaseReg>%s),\s*(?P<am2_3OffsetReg>-?%s)\]" % (Reg, Reg)
 AMode2_4 = "\[(?P<am2_4BaseReg>%s),\s*(?P<am2_4OffsetReg>%s),\s*(?:%s)\s*#\d*\]" % (Reg, Reg, ShiftOpcode)
 AMode2_5 = "\[(?P<am2_5BaseReg>%s)\],\s*#(?P<am2_5ImedOff>-?\d*)" % (Reg)
-AMode2_6 = "\[(?P<am2_6BaseReg>%s)\],\s*-?(?:%s)" % (Reg, Reg)
-AMode2_7 = "\[(?P<am2_7BaseReg>%s)\],\s*(?:%s),\s*(?:%s)\s*#\d*" % (Reg, Reg, ShiftOpcode)
+AMode2_6 = "\[(?P<am2_6BaseReg>%s)\],\s*-?(?P<am2_6OffsetReg>%s)" % (Reg, Reg)
+AMode2_7 = "\[(?P<am2_7BaseReg>%s)\],\s*(?P<am2_7OffsetReg>%s),\s*(?:%s)\s*#\d*" % (Reg, Reg, ShiftOpcode)
 
 AMode2 = ("(?:%s)|(?:%s)|(?:%s)|(?:%s)|(?:%s)|(?:%s)|(?:%s)" % (AMode2_1, 
                                                                 AMode2_2, 
@@ -59,7 +59,7 @@ re_loadInst = re.compile("\s*ldrs?(?:%s)?(?:%s)?\s*(?P<destReg>%s),\s*(?:%s)(?:%
 re_storeInst = re.compile("\s*strs?(?:%s)?(?:%s)?\s*(?P<destReg>%s),\s*(?:%s)(?:%s)" % 
                          (LoadStoreType, Cond, Reg, AMode2, EndLine))
 
-re_cmpInst = re.compile("\s*(?:cmp|cmn)\s*(?:%s),\s*(?:%s)(?:%s)" % 
+re_cmpInst = re.compile("\s*(?:cmp|cmn)\s*(?P<op1Reg>%s),\s*(?:%s)(?:%s)" % 
                         (Reg, Operand2, EndLine))
 
 re_pushInst = re.compile("\s*push\s*\{(?P<pushRegs>(?:%s)(?:,\s*(?:%s))*)\}(?:%s)" % 

instrument/examples/adpcm/instrumented/adpcm_IR.c

@@ -11,6 +11,7 @@
 #include "cacheSim.h"
 extern unsigned long SP;
 extern unsigned long long memAccessCycles;
+extern unsigned long long pipelineCycles;
 
 /***********************************************************
 Copyright 1992 by Stichting Mathematisch Centrum, Amsterdam, The
@@ -120,6 +121,7 @@ memAccessCycles += simDCache(0x4a8, 1);  // PC Relative Load
 memAccessCycles += simICache(0x36c, 44);
 // TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247
 // TODO: UnmappedLS: Load GlobalVar coder_1_state at line 249
+pipelineCycles += 23;
   valpred = state->valprev;
   memAccessCycles += simDCache(state_addr, 1);
   index = state->index;
@@ -138,6 +140,7 @@ memAccessCycles += simDCache(0x4a8, 1);  // PC Relative Load
 memAccessCycles += simDCache((SP + outp_addr), 0);
 // Simulating I Cache for obj block 1
 memAccessCycles += simICache(0x398, 32);
+pipelineCycles += 15;
   outp =  outdata;
   memAccessCycles += simDCache(outdata_addr, 1);
   ivtmp_28 = 0;
@@ -147,6 +150,7 @@ memAccessCycles += simICache(0x398, 32);
 adpcm_coderbb_4:
 //  # PRED: 18 [91.0%]  (true,exec) 3 [100.0%]  (fallthru,exec)
 memAccessCycles += simDCache((SP + 0x4), 1);  // Reading Spilt Register
+pipelineCycles += 48;
   diff = (int) *(short int *)((uintptr_t)indata + (uintptr_t)ivtmp_28) - valpred;
   memAccessCycles += simDCache(indata_addr + (sizeof(short ) * (+ivtmp_28)), 1);
   if (diff < 0)
@@ -289,6 +293,7 @@ memAccessCycles += simICache(0x3b8, 200);
 
 adpcm_coderbb_19:
 //  # PRED: 18 [9.0%]  (false,exec)
+pipelineCycles += 10;
   if (bufferstep == 0)
     goto adpcm_coderbb_20;
   else
@@ -312,6 +317,7 @@ memAccessCycles += simDCache((SP + 0xc), 1);  // Reading Spilt Register
 memAccessCycles += simICache(0x490, 24);
 // TODO: UnmappedLS: Store GlobalVar coder_1_state at line 317
 // TODO: UnmappedLS: Store GlobalVar coder_1_state at line 318
+pipelineCycles += 19;
   state->valprev = (short int) (short int) valpred;
   memAccessCycles += simDCache(state_addr, 0);
   state->index = (char) (char) index;

instrument/examples/adpcm/instrumented/my_ctop_IR.c

@@ -11,6 +11,7 @@
 #include "cacheSim.h"
 unsigned long SP = 0x1234;
 unsigned long long memAccessCycles = 0;
+unsigned long long pipelineCycles = 0;
 
 /*
 ** Timing - Test timing on adpcm coder and decoder.
@@ -69,6 +70,7 @@ memAccessCycles += simDCache(ARR_SIZE_addr, 1);
 memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0);
 // Simulating I Cache for obj block 0
 memAccessCycles += simICache(0x200, 36);
+pipelineCycles += 27;
   ARR_SIZE_0 = ARR_SIZE;
   j = ARR_SIZE_0 / 10240;
   if (j != 0)
@@ -86,12 +88,14 @@ memAccessCycles += simDCache(0x364, 1);  // PC Relative Load
 memAccessCycles += simDCache(0x368, 1);  // PC Relative Load
 // Simulating I Cache for obj block 1
 memAccessCycles += simICache(0x224, 40);
+pipelineCycles += 21;
   end_43 = 0;
   count = 0;
 //  # SUCC: 3 [100.0%]  (fallthru)
 
 mainbb_3:
 //  # PRED: 13 [100.0%]  (fallthru) 14 [100.0%]  (fallthru)
+pipelineCycles += 9;
   end_46 = end_43 + 10240;
   if (end_43 < end_46)
     goto mainbb_4;
@@ -104,6 +108,7 @@ mainbb_4:
 memAccessCycles += simDCache((SP + 0x4), 1);  // Reading Spilt Register
 // Simulating I Cache for obj block 3
 memAccessCycles += simICache(0x258, 20);
+pipelineCycles += 13;
   i_45 = (int) end_43;
   ivtmp_34 = (uintptr_t)&in_Data[i_45];
   end_44 = end_43;
@@ -115,6 +120,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0);
 // Simulating I Cache for obj block 4
 memAccessCycles += simICache(0x26c, 36);
 // TODO: UnmappedLS: Load GlobalVar in_Data at line 179
+pipelineCycles += 16;
   pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
   i_45 = i_45 + 1;
   end_44 = (long unsigned int) i_45;
@@ -129,6 +135,7 @@ mainbb_6:
 //  # PRED: 5 [1.0%]  (false,exec) 3 [1.0%]  (false,exec)
 // Simulating I Cache for obj block 5
 memAccessCycles += simICache(0x290, 40);
+pipelineCycles += 14;
   adpcm_coder (&pcmdata, pcmdata_addr,  &adpcmdata, adpcmdata_addr,  10240,  &coder_1_state, coder_1_state_addr);
   count = count + 1;
   if (j > count)
@@ -151,6 +158,7 @@ memAccessCycles += simDCache(0x358, 1);  // PC Relative Load
 memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1);
 // Simulating I Cache for obj block 6
 memAccessCycles += simICache(0x2b8, 32);
+pipelineCycles += 19;
   if (ARR_SIZE_0 % 10240 != 0)
     goto mainbb_8;
   else
@@ -162,6 +170,7 @@ mainbb_8:
 memAccessCycles += simDCache(0x354, 1);  // PC Relative Load
 // Simulating I Cache for obj block 7
 memAccessCycles += simICache(0x2d8, 24);
+pipelineCycles += 14;
   start_40 = j * 10240;
   memAccessCycles += simDCache(ARR_SIZE_addr, 1);
   end = ARR_SIZE;
@@ -177,6 +186,7 @@ memAccessCycles += simDCache(0x35c, 1);  // PC Relative Load
 memAccessCycles += simDCache(0x360, 1);  // PC Relative Load
 // Simulating I Cache for obj block 8
 memAccessCycles += simICache(0x2f0, 28);
+pipelineCycles += 13;
   i = (int) start_40;
   ivtmp_28 = (uintptr_t)&in_Data[i];
   D_2229 = (int) end;
@@ -189,6 +199,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0);
 // Simulating I Cache for obj block 9
 memAccessCycles += simICache(0x30c, 36);
 // TODO: UnmappedLS: Inaccurately Matched Load at line 219
+pipelineCycles += 16;
   pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
   i = i + 1;
   start = (long unsigned int) i;
@@ -206,6 +217,7 @@ memAccessCycles += simDCache(0x364, 1);  // PC Relative Load
 memAccessCycles += simDCache(0x368, 1);  // PC Relative Load
 // Simulating I Cache for obj block 10
 memAccessCycles += simICache(0x330, 20);
+pipelineCycles += 11;
   adpcm_coder (&pcmdata, pcmdata_addr,  &adpcmdata, adpcmdata_addr,  (int) (end - start_40),  &coder_1_state, coder_1_state_addr);
 //  # SUCC: 12 [100.0%]  (fallthru,exec)
 
@@ -214,7 +226,9 @@ mainbb_12:
 // Simulating I Cache for obj block 11
 memAccessCycles += simICache(0x344, 16);
 printf("memAccessCycles = \%llu\n", memAccessCycles);
+printf("pipelineCycles = \%llu\n", pipelineCycles);
 cacheSimFini();
+pipelineCycles += 18;
   return 0;
 //  # SUCC: EXIT [100.0%] 
 

instrument/cacheSimInstrument.py → instrument/instrument.py

@@ -2,13 +2,15 @@ import logging
 from optparse import OptionParser
 from subprocess import call
 import linecache as lc
+from collections import OrderedDict
 
 from load_store_info import *
 from match_cfg import match_cfg
 from gdb_info import *
 from cGrammar import parse_statement
 from irc_regex import *
-from collections import OrderedDict
+from pipeline_sim import *
+from annotation import *
 
 import re
 
@@ -21,16 +23,6 @@ def find(f, seq):
             return item
     return None
     
-class Annotation:
-    def __init__(self, annotation, fileName, lineNum, replace = False):
-        self.fileName = fileName
-        self.lineNum = lineNum
-        self.annotation = annotation
-        self.replace = replace
-        
-    def debug(self):
-        logging.debug("%s:%d: %s" % (self.fileName, self.lineNum, self.annotation))
-    
 def getListLocalVarInFunc(listLocalVariables, functionName):
     listLocalVarInFunc = []
     for localVar in listLocalVariables:
@@ -38,19 +30,8 @@ def getListLocalVarInFunc(listLocalVariables, functionName):
             listLocalVarInFunc.append(localVar)
     return listLocalVarInFunc
 
-def debugDictAnnot(dictAnnot):
-    for lineNum in dictAnnot.iterkeys():
-        for annot in dictAnnot[lineNum]:
-            annot.debug()
-
-def addAnnotationToDict(dict, lineNum, annot):
-    if lineNum not in dict:
-        dict[lineNum] = [annot]
-    else:
-        for a in dict[lineNum]:
-            if a.annotation == annot.annotation and a.fileName == annot.fileName:
-                return
-        dict[lineNum].append(annot)
+# TODO : Make a new function to instrument the additional global vars needed! 
+# def annotateGlobalVar(listISCFileNames):
 
 def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables, listLocalVariables):
     dictAnnotVarFuncDecl = {}
@@ -91,6 +72,11 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables,
                         addAnnotationToDict(dictAnnotVarFuncDecl,
                                             lineNum,
                                             annot)
+                        annot_str = "unsigned long long pipelineCycles = 0;"
+                        annot = Annotation(annot_str, ISCFileName, lineNum, False)
+                        addAnnotationToDict(dictAnnotVarFuncDecl,
+                                            lineNum,
+                                            annot)
                     else:
                         annot_str = "extern unsigned long SP;"
                         annot = Annotation(annot_str, ISCFileName, lineNum, False)
@@ -102,6 +88,11 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables,
                         addAnnotationToDict(dictAnnotVarFuncDecl,
                                             lineNum,
                                             annot)
+                        annot_str = "extern unsigned long long pipelineCycles;"
+                        annot = Annotation(annot_str, ISCFileName, lineNum, False)
+                        addAnnotationToDict(dictAnnotVarFuncDecl,
+                                            lineNum,
+                                            annot)
             
             if inMultiLineVarInit == 1:
                 m = re_VarDeclInitMultiLineEnd.match(line)
@@ -303,6 +294,8 @@ def annotateVarFuncDecl(listISCFileNames, listISCFunctions, listGlobalVariables,
     debugDictAnnot(dictAnnotVarFuncDecl)
     return dictAnnotVarFuncDecl
     
+    # TODO : Annotate Push Pop Operations for DCache Access to Stack!
+    
 def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGlobalVariables, listLocalVariables):
     dictAnnotLoadStore = {}
     
@@ -445,6 +438,9 @@ def annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGl
                     annot_str = 'printf("memAccessCycles = \%llu\\n", memAccessCycles);'
                     annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False)
                     addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot)
+                    annot_str = 'printf("pipelineCycles = \%llu\\n", pipelineCycles);'
+                    annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False)
+                    addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot)
                     annot_str = 'cacheSimFini();'
                     annot = Annotation(annot_str, funcISC.fileName, returnLineNumber-1, False)
                     addAnnotationToDict(dictAnnotLoadStore, returnLineNumber-1, annot)
@@ -553,7 +549,11 @@ def instrumentCache(listISCFileNames, listObjdumpFileNames, listBinaryFileNames,
     
     dictAnnotLoadStore = annotateLoadStore(listISCFunctions, listObjdumpFunctions, listLSInfo, listGlobalVariables, listLocalVariables)
 
+    dictAnnotPipeline = annot_pipeline_sim(listISCFunctions, listObjdumpFunctions)
+    debugDictAnnot(dictAnnotPipeline)
+
     dictAnnot = unionDict(dictAnnotVarFuncDecl, dictAnnotLoadStore)
+    dictAnnot = unionDict(dictAnnot, dictAnnotPipeline)
 
     generateAnnotatedSourceFiles(dictAnnot, listISCFileNames, insOutputPath)