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hostCompiledSimulation
Commit 0da352bb authored by Gaurav Kukreja's avatar Gaurav Kukreja
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Many important fixes 

Signed-off-by: Gaurav Kukreja's avatarGaurav Kukreja <gaurav@gauravk.in>
parent 095c2407
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Showing with 1537 additions and 15082 deletions
cache_simulator/src/cortexA5HwMod.c
View file @ 0da352bb
......@@ -66,8 +66,8 @@ cacheLine_t **L1DCache;
cacheLine_t **L1ICache;
cacheLine_t **L2Cache;
unsigned int memWriteLatency = 50;
unsigned int memReadLatency = 50;
unsigned int memWriteLatency = 55;
unsigned int memReadLatency = 55;
unsigned int memReadPrefetchLatency = 0;
unsigned long L1D_Hit_Read = 0;
......@@ -403,7 +403,7 @@ unsigned long long cortexA5_simICache(unsigned long address,
if(IS_CACHELINE_DIRTY(L2Cache[l2Index][l2InvalidSetIndex].flags))
{
// Write Back to memory!
latency += memWriteLatency;
// latency += memWriteLatency;
L2_Hit_Writeback++;
}
}
......@@ -640,7 +640,7 @@ unsigned long long cortexA5_simDCache(unsigned long address,
{
if (address == access->address + L2CacheConf.lineLenBytes)
{
if (access->sequentialAccess > 15)
if (access->sequentialAccess > 5)
{
/**
* Data would have been prefetched !!
......
instrument/examples/adpcm/instrumented/adpcm_IR.c
View file @ 0da352bb
......@@ -147,7 +147,7 @@ memAccessCycles += simICache(0x398, 32, &csim_result);
estimate_power("adpcm_coderbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
outp = outdata;
// memAccessCycles += simDCache(outdata_addr, 1, &csim_result);
memAccessCycles += simDCache(outdata_addr, 1, &csim_result);
ivtmp_28 = 0;
bufferstep = 1;
// # SUCC: 4 [100.0%] (fallthru,exec)
......@@ -275,10 +275,8 @@ memAccessCycles += simDCache((SP + outputbuffer_addr), 0, &csim_result);
adpcm_coderbb_17:
// # PRED: 15 [50.0%] (false,exec)
memAccessCycles += simDCache((SP + outputbuffer_addr), 1, &csim_result);
memAccessCycles += simDCache(outdata_addr + (unsigned long)((uintptr_t)outp - (uintptr_t)outdata), 0, &csim_result); //MANUAL
//memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
*outp = (signed char) delta_37 & 15 | (signed char) outputbuffer;
memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
outp = (uintptr_t)outp + 1;
// # SUCC: 18 [100.0%] (fallthru,exec)
......
instrument/examples/adpcm/instrumented/my_ctop_IR.c
View file @ 0da352bb
......@@ -10,7 +10,8 @@
#include "ir2c.h"
#include "cacheSim.h"
#include "branchPred.h"
unsigned long SP = 0x1fffb8;
#include "power_estimator.h"
unsigned long SP = 0x1234;
unsigned long long memAccessCycles = 0;
unsigned long long pipelineCycles = 0;
struct csim_result_t csim_result;
......@@ -62,9 +63,6 @@ int main() {
unsigned int ARR_SIZE_0;
unsigned long ARR_SIZE_0_addr = 0x0;
unsigned long ivtmp_34_addr = 0; // MANUAL
unsigned long ivtmp_28_addr = 0;
mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(&csim_result);
......@@ -121,7 +119,6 @@ estimate_power("mainbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits,
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45];
ivtmp_34_addr = in_Data_addr + (2 * i_45);
end_44 = end_43;
// # SUCC: 5 [100.0%] (fallthru,exec)
......@@ -134,11 +131,9 @@ estimate_power("mainbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits,
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
memAccessCycles += simDCache(ivtmp_34_addr, 1, &csim_result);
i_45 = i_45 + 1;
end_44 = (long unsigned int) i_45;
ivtmp_34 = ivtmp_34 + 2;
ivtmp_34_addr = ivtmp_34_addr + 2;
if (end_44 < end_46)
goto mainbb_5;
else
......@@ -208,7 +203,6 @@ estimate_power("mainbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits,
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i];
ivtmp_28_addr = in_Data_addr + (2 * i);
D_2229 = (int) end;
start = start_40;
// # SUCC: 10 [100.0%] (fallthru,exec)
......@@ -221,12 +215,10 @@ memAccessCycles += simICache(0x30c, 36, &csim_result);
estimate_power("mainbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result);
pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
i = i + 1;
start = (long unsigned int) i;
ivtmp_28 = ivtmp_28 + 2;
ivtmp_28_addr = ivtmp_28_addr + 2;
if (i != D_2229)
goto mainbb_10;
else
......
instrument/examples/adpcm/instrumented_power/adpcm_IR.c
View file @ 0da352bb
......@@ -125,7 +125,7 @@ memAccessCycles += simICache(0x36c, 44, &csim_result);
estimate_power("adpcm_coderbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 249
pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 7 : 0);
pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 5 : 0);
valpred = state->valprev;
memAccessCycles += simDCache(state_addr, 1, &csim_result);
index = state->index;
......@@ -145,7 +145,7 @@ memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x398, 32, &csim_result);
estimate_power("adpcm_coderbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 5 : 0);
outp = outdata;
// memAccessCycles += simDCache(outdata_addr, 1, &csim_result);
ivtmp_28 = 0;
......@@ -155,7 +155,7 @@ pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
adpcm_coderbb_4:
// # PRED: 18 [91.0%] (true,exec) 3 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
pipelineCycles += 48 - (enterBlock(0x106, 0x137) ? 7 : 0);
pipelineCycles += 48 - (enterBlock(0x106, 0x137) ? 5 : 0);
diff = (int) *(short int *)((uintptr_t)indata + (uintptr_t)ivtmp_28) - valpred;
memAccessCycles += simDCache(indata_addr + (+ivtmp_28), 1, &csim_result);
if (diff < 0)
......@@ -301,7 +301,7 @@ estimate_power("adpcm_coderbb_18", pipelineCycles, memAccessCycles, csim_result.
adpcm_coderbb_19:
// # PRED: 18 [9.0%] (false,exec)
pipelineCycles += 10 - (enterBlock(0x138, 0x13b) ? 7 : 0);
pipelineCycles += 10 - (enterBlock(0x138, 0x13b) ? 5 : 0);
if (bufferstep == 0)
goto adpcm_coderbb_20;
else
......@@ -328,7 +328,7 @@ memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Reg
memAccessCycles += simICache(0x490, 24, &csim_result);
// TODO: UnmappedLS: Store GlobalVar coder_1_state at line 317
// TODO: UnmappedLS: Store GlobalVar coder_1_state at line 318
pipelineCycles += 19 - (enterBlock(0x13c, 0x141) ? 7 : 0);
pipelineCycles += 19 - (enterBlock(0x13c, 0x141) ? 5 : 0);
state->valprev = (short int) (short int) valpred;
memAccessCycles += simDCache(state_addr, 0, &csim_result);
state->index = (char) (char) index;
......
instrument/examples/adpcm/instrumented_power/my_ctop_IR.c
View file @ 0da352bb
......@@ -78,7 +78,7 @@ memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0, &csim_result);
// Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 36, &csim_result);
estimate_power("mainbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 7 : 0);
pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 5 : 0);
ARR_SIZE_0 = ARR_SIZE;
j = ARR_SIZE_0 / 10240;
if (j != 0)
......@@ -97,14 +97,14 @@ memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 1
memAccessCycles += simICache(0x224, 40, &csim_result);
estimate_power("mainbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 7 : 0);
pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 5 : 0);
end_43 = 0;
count = 0;
// # SUCC: 3 [100.0%] (fallthru)
mainbb_3:
// # PRED: 13 [100.0%] (fallthru) 14 [100.0%] (fallthru)
pipelineCycles += 9 - (enterBlock(0xa9, 0xab) ? 7 : 0);
pipelineCycles += 9 - (enterBlock(0xa9, 0xab) ? 5 : 0);
end_46 = end_43 + 10240;
if (end_43 < end_46)
goto mainbb_4;
......@@ -118,7 +118,7 @@ memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Reg
// Simulating I Cache for obj block 3
memAccessCycles += simICache(0x258, 20, &csim_result);
estimate_power("mainbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 5 : 0);
i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45];
ivtmp_34_addr = in_Data_addr + (2 * i_45);
......@@ -132,7 +132,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0, &csim_resu
memAccessCycles += simICache(0x26c, 36, &csim_result);
estimate_power("mainbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 5 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
memAccessCycles += simDCache(ivtmp_34_addr, 1, &csim_result);
i_45 = i_45 + 1;
......@@ -150,7 +150,7 @@ mainbb_6:
// Simulating I Cache for obj block 5
memAccessCycles += simICache(0x290, 40, &csim_result);
estimate_power("mainbb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 7 : 0);
pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 5 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr);
count = count + 1;
if (j > count)
......@@ -175,7 +175,7 @@ memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1, &csim_result);
// Simulating I Cache for obj block 6
memAccessCycles += simICache(0x2b8, 32, &csim_result);
estimate_power("mainbb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 7 : 0);
pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 5 : 0);
if (ARR_SIZE_0 % 10240 != 0)
goto mainbb_8;
else
......@@ -188,7 +188,7 @@ memAccessCycles += simDCache(0x354, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2d8, 24, &csim_result);
estimate_power("mainbb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 7 : 0);
pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 5 : 0);
start_40 = j * 10240;
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
end = ARR_SIZE;
......@@ -205,7 +205,7 @@ memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2f0, 28, &csim_result);
estimate_power("mainbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 5 : 0);
i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i];
ivtmp_28_addr = in_Data_addr + (2 * i);
......@@ -220,7 +220,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0, &csim_res
memAccessCycles += simICache(0x30c, 36, &csim_result);
estimate_power("mainbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 5 : 0);
memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result);
pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
i = i + 1;
......@@ -241,7 +241,7 @@ memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 10
memAccessCycles += simICache(0x330, 20, &csim_result);
estimate_power("mainbb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 7 : 0);
pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 5 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr);
// # SUCC: 12 [100.0%] (fallthru,exec)
......@@ -254,7 +254,7 @@ printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini(&csim_result);
power_estimator_fini();
pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 7 : 0);
pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 5 : 0);
return 0;
// # SUCC: EXIT [100.0%]
......
instrument/examples/adpcm/instrumented_power/power_trace.dat
View file @ 0da352bb
This source diff could not be displayed because it is too large. You can view the blob instead.
instrument/examples/sha/instrumented_power/result.txt 0 → 100644
View file @ 0da352bb
06 Nov. 11:45 am
memAccessCycles = 4440193
pipelineCycles = 20502591
Statistics :
Total L1 Hits = 5406006
Total L2 Hits = 1928
Total L2 Misses = 14805
Total Prefetches = 9100
Mem Access Cycles = 4440193
L1 Data Cache
Hit Read = 2209850
Hit Writeback = 951041
Miss = 1928
L1 Instruction Cache
Hit Read = 3187056
Miss = 0
L2 Unified Cache
Hit Read = 1928
Hit Writeback = 12624
Inst. Miss = 24
Data Miss = 23881
Accesses = 4938338
L1 Hits = 0
L1 Miss = 0 (L1 Miss Rate = 0)
L2 Hits = 0
L2 Miss = 0 (L2 Miss Rate = 0)
instrument/examples/sieve/instrumented/erat_sieve_no_print_IR.c
View file @ 0da352bb
......@@ -27,7 +27,7 @@ struct test {
unsigned int v;
unsigned int k;
} m = { 1, 1 };
unsigned long m_addr = 0x7c8;
void sieve_func() {
int j_76;
......@@ -41,7 +41,6 @@ void sieve_func() {
uintptr_t D_2240;
uintptr_t D_2230;
uintptr_t ivtmp_36;
unsigned long ivtmp_36_addr; // MANUAL
int j;
int i;
unsigned int sieve[500000];
......@@ -216,7 +215,6 @@ memAccessCycles += simICache(0x31c, 12, &csim_result);
estimate_power("sieve_funcbb_13", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 10 - (enterBlock(0xdd, 0xdf) ? 7 : 0);
ivtmp_36 = (uintptr_t)&results;
ivtmp_36_addr = results_addr;
D_2230 = ivtmp_36 + 1999996;
// # SUCC: 14 [100.0%] (fallthru,exec)
......@@ -227,7 +225,6 @@ memAccessCycles += simICache(0x328, 12, &csim_result);
estimate_power("sieve_funcbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar results at line 224
pipelineCycles += 8 - (enterBlock(0xe0, 0xe2) ? 7 : 0);
memAccessCycles += simDCache(ivtmp_36_addr + 4, 1, &csim_result);
if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0)
goto sieve_funcbb_16;
else
......@@ -241,7 +238,6 @@ memAccessCycles += simICache(0x334, 12, &csim_result);
estimate_power("sieve_funcbb_15", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0xe3, 0xe5) ? 7 : 0);
ivtmp_36 = ivtmp_36 + 4;
ivtmp_36_addr = ivtmp_36_addr + 4;
if (ivtmp_36 != D_2230)
goto sieve_funcbb_14;
else
......
instrument/pipeline_sim.py
View file @ 0da352bb
......@@ -416,7 +416,7 @@ def annot_pipeline_sim(listISCFunctions,
# Block Done!
blockIndISC = blockObj.mapsTo[0]
blockISC = funcISC.cfg.listBlocks[blockIndISC]
annot_str = "pipelineCycles += %d - (enterBlock(0x%x, 0x%x) ? 7 : 0);" % (currBlockCycles,
annot_str = "pipelineCycles += %d - (enterBlock(0x%x, 0x%x) ? 5 : 0);" % (currBlockCycles,
blockObj.startLine,
blockObj.endLine)
annot = Annotation(annot_str,
......
instrument/sha.sh
View file @ 0da352bb
#!/bin/sh
python instrument.py -i examples/sha/in_small.h -i examples/sha/ir2c.h -i examples/sha/my_defines.h -i examples/sha/my_mem.h -i examples/sha/my_mem_IR.c -i examples/sha/my_variable.h -i examples/sha/sha_driver_IR.c -i examples/sha/sha.h -i examples/sha/sha_IR.c -o examples/sha/sha_driver_IR.objdump -b examples/sha/sha_driver_IR.elf -p examples/sha/instrumented/
python instrument.py -i examples/sha/in_small.h -i examples/sha/ir2c.h -i examples/sha/my_defines.h -i examples/sha/my_mem.h -i examples/sha/my_mem_IR.c -i examples/sha/my_variable.h -i examples/sha/sha_driver_IR.c -i examples/sha/sha.h -i examples/sha/sha_IR.c -o examples/sha/sha_driver_IR.objdump -b examples/sha/sha_driver_IR.elf -p examples/sha/instrumented_power/
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