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hostCompiledSimulation
Commit 0da352bb authored by Gaurav Kukreja's avatar Gaurav Kukreja
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Many important fixes 

Signed-off-by: Gaurav Kukreja's avatarGaurav Kukreja <gaurav@gauravk.in>
parent 095c2407
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Showing with 1537 additions and 15082 deletions
cache_simulator/src/cortexA5HwMod.c
View file @ 0da352bb
...@@ -66,8 +66,8 @@ cacheLine_t **L1DCache; ...@@ -66,8 +66,8 @@ cacheLine_t **L1DCache;
cacheLine_t **L1ICache; cacheLine_t **L1ICache;
cacheLine_t **L2Cache; cacheLine_t **L2Cache;
unsigned int memWriteLatency = 50; unsigned int memWriteLatency = 55;
unsigned int memReadLatency = 50; unsigned int memReadLatency = 55;
unsigned int memReadPrefetchLatency = 0; unsigned int memReadPrefetchLatency = 0;
unsigned long L1D_Hit_Read = 0; unsigned long L1D_Hit_Read = 0;
...@@ -403,7 +403,7 @@ unsigned long long cortexA5_simICache(unsigned long address, ...@@ -403,7 +403,7 @@ unsigned long long cortexA5_simICache(unsigned long address,
if(IS_CACHELINE_DIRTY(L2Cache[l2Index][l2InvalidSetIndex].flags)) if(IS_CACHELINE_DIRTY(L2Cache[l2Index][l2InvalidSetIndex].flags))
{ {
// Write Back to memory! // Write Back to memory!
latency += memWriteLatency; // latency += memWriteLatency;
L2_Hit_Writeback++; L2_Hit_Writeback++;
} }
} }
...@@ -640,7 +640,7 @@ unsigned long long cortexA5_simDCache(unsigned long address, ...@@ -640,7 +640,7 @@ unsigned long long cortexA5_simDCache(unsigned long address,
{ {
if (address == access->address + L2CacheConf.lineLenBytes) if (address == access->address + L2CacheConf.lineLenBytes)
{ {
if (access->sequentialAccess > 15) if (access->sequentialAccess > 5)
{ {
/** /**
* Data would have been prefetched !! * Data would have been prefetched !!
......
instrument/examples/adpcm/instrumented/adpcm_IR.c
View file @ 0da352bb
...@@ -147,7 +147,7 @@ memAccessCycles += simICache(0x398, 32, &csim_result); ...@@ -147,7 +147,7 @@ memAccessCycles += simICache(0x398, 32, &csim_result);
estimate_power("adpcm_coderbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("adpcm_coderbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0); pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
outp = outdata; outp = outdata;
// memAccessCycles += simDCache(outdata_addr, 1, &csim_result); memAccessCycles += simDCache(outdata_addr, 1, &csim_result);
ivtmp_28 = 0; ivtmp_28 = 0;
bufferstep = 1; bufferstep = 1;
// # SUCC: 4 [100.0%] (fallthru,exec) // # SUCC: 4 [100.0%] (fallthru,exec)
...@@ -275,10 +275,8 @@ memAccessCycles += simDCache((SP + outputbuffer_addr), 0, &csim_result); ...@@ -275,10 +275,8 @@ memAccessCycles += simDCache((SP + outputbuffer_addr), 0, &csim_result);
adpcm_coderbb_17: adpcm_coderbb_17:
// # PRED: 15 [50.0%] (false,exec) // # PRED: 15 [50.0%] (false,exec)
memAccessCycles += simDCache((SP + outputbuffer_addr), 1, &csim_result); memAccessCycles += simDCache((SP + outputbuffer_addr), 1, &csim_result);
memAccessCycles += simDCache(outdata_addr + (unsigned long)((uintptr_t)outp - (uintptr_t)outdata), 0, &csim_result); //MANUAL memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
//memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
*outp = (signed char) delta_37 & 15 | (signed char) outputbuffer; *outp = (signed char) delta_37 & 15 | (signed char) outputbuffer;
memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
outp = (uintptr_t)outp + 1; outp = (uintptr_t)outp + 1;
// # SUCC: 18 [100.0%] (fallthru,exec) // # SUCC: 18 [100.0%] (fallthru,exec)
......
instrument/examples/adpcm/instrumented/my_ctop_IR.c
View file @ 0da352bb
...@@ -10,7 +10,8 @@ ...@@ -10,7 +10,8 @@
#include "ir2c.h" #include "ir2c.h"
#include "cacheSim.h" #include "cacheSim.h"
#include "branchPred.h" #include "branchPred.h"
unsigned long SP = 0x1fffb8; #include "power_estimator.h"
unsigned long SP = 0x1234;
unsigned long long memAccessCycles = 0; unsigned long long memAccessCycles = 0;
unsigned long long pipelineCycles = 0; unsigned long long pipelineCycles = 0;
struct csim_result_t csim_result; struct csim_result_t csim_result;
...@@ -62,9 +63,6 @@ int main() { ...@@ -62,9 +63,6 @@ int main() {
unsigned int ARR_SIZE_0; unsigned int ARR_SIZE_0;
unsigned long ARR_SIZE_0_addr = 0x0; unsigned long ARR_SIZE_0_addr = 0x0;
unsigned long ivtmp_34_addr = 0; // MANUAL
unsigned long ivtmp_28_addr = 0;
mainbb_2: mainbb_2:
// # PRED: ENTRY [100.0%] (fallthru,exec) // # PRED: ENTRY [100.0%] (fallthru,exec)
cacheSimInit(&csim_result); cacheSimInit(&csim_result);
...@@ -121,7 +119,6 @@ estimate_power("mainbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, ...@@ -121,7 +119,6 @@ estimate_power("mainbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits,
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0); pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0);
i_45 = (int) end_43; i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45]; ivtmp_34 = (uintptr_t)&in_Data[i_45];
ivtmp_34_addr = in_Data_addr + (2 * i_45);
end_44 = end_43; end_44 = end_43;
// # SUCC: 5 [100.0%] (fallthru,exec) // # SUCC: 5 [100.0%] (fallthru,exec)
...@@ -134,11 +131,9 @@ estimate_power("mainbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, ...@@ -134,11 +131,9 @@ estimate_power("mainbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits,
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179 // TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0); pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34); pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
memAccessCycles += simDCache(ivtmp_34_addr, 1, &csim_result);
i_45 = i_45 + 1; i_45 = i_45 + 1;
end_44 = (long unsigned int) i_45; end_44 = (long unsigned int) i_45;
ivtmp_34 = ivtmp_34 + 2; ivtmp_34 = ivtmp_34 + 2;
ivtmp_34_addr = ivtmp_34_addr + 2;
if (end_44 < end_46) if (end_44 < end_46)
goto mainbb_5; goto mainbb_5;
else else
...@@ -208,7 +203,6 @@ estimate_power("mainbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, ...@@ -208,7 +203,6 @@ estimate_power("mainbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits,
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0); pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0);
i = (int) start_40; i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i]; ivtmp_28 = (uintptr_t)&in_Data[i];
ivtmp_28_addr = in_Data_addr + (2 * i);
D_2229 = (int) end; D_2229 = (int) end;
start = start_40; start = start_40;
// # SUCC: 10 [100.0%] (fallthru,exec) // # SUCC: 10 [100.0%] (fallthru,exec)
...@@ -221,12 +215,10 @@ memAccessCycles += simICache(0x30c, 36, &csim_result); ...@@ -221,12 +215,10 @@ memAccessCycles += simICache(0x30c, 36, &csim_result);
estimate_power("mainbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Inaccurately Matched Load at line 219 // TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0); pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0);
memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result);
pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28); pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
i = i + 1; i = i + 1;
start = (long unsigned int) i; start = (long unsigned int) i;
ivtmp_28 = ivtmp_28 + 2; ivtmp_28 = ivtmp_28 + 2;
ivtmp_28_addr = ivtmp_28_addr + 2;
if (i != D_2229) if (i != D_2229)
goto mainbb_10; goto mainbb_10;
else else
......
instrument/examples/adpcm/instrumented_power/adpcm_IR.c
View file @ 0da352bb
...@@ -125,7 +125,7 @@ memAccessCycles += simICache(0x36c, 44, &csim_result); ...@@ -125,7 +125,7 @@ memAccessCycles += simICache(0x36c, 44, &csim_result);
estimate_power("adpcm_coderbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("adpcm_coderbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247 // TODO: UnmappedLS: Load GlobalVar coder_1_state at line 247
// TODO: UnmappedLS: Load GlobalVar coder_1_state at line 249 // TODO: UnmappedLS: Load GlobalVar coder_1_state at line 249
pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 7 : 0); pipelineCycles += 23 - (enterBlock(0xf3, 0xfd) ? 5 : 0);
valpred = state->valprev; valpred = state->valprev;
memAccessCycles += simDCache(state_addr, 1, &csim_result); memAccessCycles += simDCache(state_addr, 1, &csim_result);
index = state->index; index = state->index;
...@@ -145,7 +145,7 @@ memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result); ...@@ -145,7 +145,7 @@ memAccessCycles += simDCache((SP + outp_addr), 0, &csim_result);
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x398, 32, &csim_result); memAccessCycles += simICache(0x398, 32, &csim_result);
estimate_power("adpcm_coderbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("adpcm_coderbb_3", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0); pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 5 : 0);
outp = outdata; outp = outdata;
// memAccessCycles += simDCache(outdata_addr, 1, &csim_result); // memAccessCycles += simDCache(outdata_addr, 1, &csim_result);
ivtmp_28 = 0; ivtmp_28 = 0;
...@@ -155,7 +155,7 @@ pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0); ...@@ -155,7 +155,7 @@ pipelineCycles += 15 - (enterBlock(0xfe, 0x105) ? 7 : 0);
adpcm_coderbb_4: adpcm_coderbb_4:
// # PRED: 18 [91.0%] (true,exec) 3 [100.0%] (fallthru,exec) // # PRED: 18 [91.0%] (true,exec) 3 [100.0%] (fallthru,exec)
memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Register
pipelineCycles += 48 - (enterBlock(0x106, 0x137) ? 7 : 0); pipelineCycles += 48 - (enterBlock(0x106, 0x137) ? 5 : 0);
diff = (int) *(short int *)((uintptr_t)indata + (uintptr_t)ivtmp_28) - valpred; diff = (int) *(short int *)((uintptr_t)indata + (uintptr_t)ivtmp_28) - valpred;
memAccessCycles += simDCache(indata_addr + (+ivtmp_28), 1, &csim_result); memAccessCycles += simDCache(indata_addr + (+ivtmp_28), 1, &csim_result);
if (diff < 0) if (diff < 0)
...@@ -301,7 +301,7 @@ estimate_power("adpcm_coderbb_18", pipelineCycles, memAccessCycles, csim_result. ...@@ -301,7 +301,7 @@ estimate_power("adpcm_coderbb_18", pipelineCycles, memAccessCycles, csim_result.
adpcm_coderbb_19: adpcm_coderbb_19:
// # PRED: 18 [9.0%] (false,exec) // # PRED: 18 [9.0%] (false,exec)
pipelineCycles += 10 - (enterBlock(0x138, 0x13b) ? 7 : 0); pipelineCycles += 10 - (enterBlock(0x138, 0x13b) ? 5 : 0);
if (bufferstep == 0) if (bufferstep == 0)
goto adpcm_coderbb_20; goto adpcm_coderbb_20;
else else
...@@ -328,7 +328,7 @@ memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Reg ...@@ -328,7 +328,7 @@ memAccessCycles += simDCache((SP + 0xc), 1, &csim_result); // Reading Spilt Reg
memAccessCycles += simICache(0x490, 24, &csim_result); memAccessCycles += simICache(0x490, 24, &csim_result);
// TODO: UnmappedLS: Store GlobalVar coder_1_state at line 317 // TODO: UnmappedLS: Store GlobalVar coder_1_state at line 317
// TODO: UnmappedLS: Store GlobalVar coder_1_state at line 318 // TODO: UnmappedLS: Store GlobalVar coder_1_state at line 318
pipelineCycles += 19 - (enterBlock(0x13c, 0x141) ? 7 : 0); pipelineCycles += 19 - (enterBlock(0x13c, 0x141) ? 5 : 0);
state->valprev = (short int) (short int) valpred; state->valprev = (short int) (short int) valpred;
memAccessCycles += simDCache(state_addr, 0, &csim_result); memAccessCycles += simDCache(state_addr, 0, &csim_result);
state->index = (char) (char) index; state->index = (char) (char) index;
......
instrument/examples/adpcm/instrumented_power/my_ctop_IR.c
View file @ 0da352bb
...@@ -78,7 +78,7 @@ memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0, &csim_result); ...@@ -78,7 +78,7 @@ memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 0, &csim_result);
// Simulating I Cache for obj block 0 // Simulating I Cache for obj block 0
memAccessCycles += simICache(0x200, 36, &csim_result); memAccessCycles += simICache(0x200, 36, &csim_result);
estimate_power("mainbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_2", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 7 : 0); pipelineCycles += 27 - (enterBlock(0x96, 0x9e) ? 5 : 0);
ARR_SIZE_0 = ARR_SIZE; ARR_SIZE_0 = ARR_SIZE;
j = ARR_SIZE_0 / 10240; j = ARR_SIZE_0 / 10240;
if (j != 0) if (j != 0)
...@@ -97,14 +97,14 @@ memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load ...@@ -97,14 +97,14 @@ memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 1 // Simulating I Cache for obj block 1
memAccessCycles += simICache(0x224, 40, &csim_result); memAccessCycles += simICache(0x224, 40, &csim_result);
estimate_power("mainbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 7 : 0); pipelineCycles += 21 - (enterBlock(0x9f, 0xa8) ? 5 : 0);
end_43 = 0; end_43 = 0;
count = 0; count = 0;
// # SUCC: 3 [100.0%] (fallthru) // # SUCC: 3 [100.0%] (fallthru)
mainbb_3: mainbb_3:
// # PRED: 13 [100.0%] (fallthru) 14 [100.0%] (fallthru) // # PRED: 13 [100.0%] (fallthru) 14 [100.0%] (fallthru)
pipelineCycles += 9 - (enterBlock(0xa9, 0xab) ? 7 : 0); pipelineCycles += 9 - (enterBlock(0xa9, 0xab) ? 5 : 0);
end_46 = end_43 + 10240; end_46 = end_43 + 10240;
if (end_43 < end_46) if (end_43 < end_46)
goto mainbb_4; goto mainbb_4;
...@@ -118,7 +118,7 @@ memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Reg ...@@ -118,7 +118,7 @@ memAccessCycles += simDCache((SP + 0x4), 1, &csim_result); // Reading Spilt Reg
// Simulating I Cache for obj block 3 // Simulating I Cache for obj block 3
memAccessCycles += simICache(0x258, 20, &csim_result); memAccessCycles += simICache(0x258, 20, &csim_result);
estimate_power("mainbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_4", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 7 : 0); pipelineCycles += 13 - (enterBlock(0xac, 0xb0) ? 5 : 0);
i_45 = (int) end_43; i_45 = (int) end_43;
ivtmp_34 = (uintptr_t)&in_Data[i_45]; ivtmp_34 = (uintptr_t)&in_Data[i_45];
ivtmp_34_addr = in_Data_addr + (2 * i_45); ivtmp_34_addr = in_Data_addr + (2 * i_45);
...@@ -132,7 +132,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0, &csim_resu ...@@ -132,7 +132,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (end_44-end_43)), 0, &csim_resu
memAccessCycles += simICache(0x26c, 36, &csim_result); memAccessCycles += simICache(0x26c, 36, &csim_result);
estimate_power("mainbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_5", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar in_Data at line 179 // TODO: UnmappedLS: Load GlobalVar in_Data at line 179
pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 7 : 0); pipelineCycles += 16 - (enterBlock(0xb1, 0xb9) ? 5 : 0);
pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34); pcmdata[end_44 - end_43] = *(short int*)((uintptr_t)ivtmp_34);
memAccessCycles += simDCache(ivtmp_34_addr, 1, &csim_result); memAccessCycles += simDCache(ivtmp_34_addr, 1, &csim_result);
i_45 = i_45 + 1; i_45 = i_45 + 1;
...@@ -150,7 +150,7 @@ mainbb_6: ...@@ -150,7 +150,7 @@ mainbb_6:
// Simulating I Cache for obj block 5 // Simulating I Cache for obj block 5
memAccessCycles += simICache(0x290, 40, &csim_result); memAccessCycles += simICache(0x290, 40, &csim_result);
estimate_power("mainbb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_6", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 7 : 0); pipelineCycles += 14 - (enterBlock(0xba, 0xc3) ? 5 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr); adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, 10240, &coder_1_state, coder_1_state_addr);
count = count + 1; count = count + 1;
if (j > count) if (j > count)
...@@ -175,7 +175,7 @@ memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1, &csim_result); ...@@ -175,7 +175,7 @@ memAccessCycles += simDCache((SP + ARR_SIZE_0_addr), 1, &csim_result);
// Simulating I Cache for obj block 6 // Simulating I Cache for obj block 6
memAccessCycles += simICache(0x2b8, 32, &csim_result); memAccessCycles += simICache(0x2b8, 32, &csim_result);
estimate_power("mainbb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_7", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 7 : 0); pipelineCycles += 19 - (enterBlock(0xc4, 0xcb) ? 5 : 0);
if (ARR_SIZE_0 % 10240 != 0) if (ARR_SIZE_0 % 10240 != 0)
goto mainbb_8; goto mainbb_8;
else else
...@@ -188,7 +188,7 @@ memAccessCycles += simDCache(0x354, 1, &csim_result); // PC Relative Load ...@@ -188,7 +188,7 @@ memAccessCycles += simDCache(0x354, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 7 // Simulating I Cache for obj block 7
memAccessCycles += simICache(0x2d8, 24, &csim_result); memAccessCycles += simICache(0x2d8, 24, &csim_result);
estimate_power("mainbb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_8", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 7 : 0); pipelineCycles += 14 - (enterBlock(0xcc, 0xd1) ? 5 : 0);
start_40 = j * 10240; start_40 = j * 10240;
memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result); memAccessCycles += simDCache(ARR_SIZE_addr, 1, &csim_result);
end = ARR_SIZE; end = ARR_SIZE;
...@@ -205,7 +205,7 @@ memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load ...@@ -205,7 +205,7 @@ memAccessCycles += simDCache(0x360, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 8 // Simulating I Cache for obj block 8
memAccessCycles += simICache(0x2f0, 28, &csim_result); memAccessCycles += simICache(0x2f0, 28, &csim_result);
estimate_power("mainbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_9", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 7 : 0); pipelineCycles += 13 - (enterBlock(0xd2, 0xd8) ? 5 : 0);
i = (int) start_40; i = (int) start_40;
ivtmp_28 = (uintptr_t)&in_Data[i]; ivtmp_28 = (uintptr_t)&in_Data[i];
ivtmp_28_addr = in_Data_addr + (2 * i); ivtmp_28_addr = in_Data_addr + (2 * i);
...@@ -220,7 +220,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0, &csim_res ...@@ -220,7 +220,7 @@ memAccessCycles += simDCache(pcmdata_addr + (2 * (start-start_40)), 0, &csim_res
memAccessCycles += simICache(0x30c, 36, &csim_result); memAccessCycles += simICache(0x30c, 36, &csim_result);
estimate_power("mainbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_10", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Inaccurately Matched Load at line 219 // TODO: UnmappedLS: Inaccurately Matched Load at line 219
pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 7 : 0); pipelineCycles += 16 - (enterBlock(0xd9, 0xe1) ? 5 : 0);
memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result); memAccessCycles += simDCache(ivtmp_28_addr, 1, &csim_result);
pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28); pcmdata[start - start_40] = *(short int*)((uintptr_t)ivtmp_28);
i = i + 1; i = i + 1;
...@@ -241,7 +241,7 @@ memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load ...@@ -241,7 +241,7 @@ memAccessCycles += simDCache(0x368, 1, &csim_result); // PC Relative Load
// Simulating I Cache for obj block 10 // Simulating I Cache for obj block 10
memAccessCycles += simICache(0x330, 20, &csim_result); memAccessCycles += simICache(0x330, 20, &csim_result);
estimate_power("mainbb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("mainbb_11", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 7 : 0); pipelineCycles += 11 - (enterBlock(0xe2, 0xe6) ? 5 : 0);
adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr); adpcm_coder (&pcmdata, pcmdata_addr, &adpcmdata, adpcmdata_addr, (int) (end - start_40), &coder_1_state, coder_1_state_addr);
// # SUCC: 12 [100.0%] (fallthru,exec) // # SUCC: 12 [100.0%] (fallthru,exec)
...@@ -254,7 +254,7 @@ printf("memAccessCycles = \%llu\n", memAccessCycles); ...@@ -254,7 +254,7 @@ printf("memAccessCycles = \%llu\n", memAccessCycles);
printf("pipelineCycles = \%llu\n", pipelineCycles); printf("pipelineCycles = \%llu\n", pipelineCycles);
cacheSimFini(&csim_result); cacheSimFini(&csim_result);
power_estimator_fini(); power_estimator_fini();
pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 7 : 0); pipelineCycles += 18 - (enterBlock(0xe7, 0xea) ? 5 : 0);
return 0; return 0;
// # SUCC: EXIT [100.0%] // # SUCC: EXIT [100.0%]
......
instrument/examples/adpcm/instrumented_power/power_trace.dat
View file @ 0da352bb
This source diff could not be displayed because it is too large. You can view the blob instead.
instrument/examples/sha/instrumented_power/power_trace.dat
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sha_transformbb_10, 562332, 91.620324 sha_updatebb_6, 5603487, 94.918209
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sha_transformbb_5, 2295937, 91.699716
sha_transformbb_7, 2305953, 91.570339
sha_transformbb_9, 2315965, 91.671118
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sha_transformbb_7, 2366693, 91.892095
sha_transformbb_14, 2376707, 91.684309
sha_transformbb_10, 2386708, 91.599790
sha_transformbb_17, 2396719, 91.680448
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sha_transformbb_3, 2416840, 92.677100
sha_transformbb_5, 2426851, 91.699716
sha_transformbb_7, 2436864, 91.518589
sha_transformbb_9, 2446874, 91.673337
sha_transformbb_10, 2456877, 91.654419
sha_transformbb_17, 2466886, 91.682669
sha_transformbb_3, 2477606, 92.437030
sha_transformbb_5, 2487622, 91.722242
sha_transformbb_7, 2497663, 91.840658
sha_transformbb_9, 2507676, 91.629778
sha_transformbb_10, 2517687, 91.566867
sha_transformbb_10, 2527701, 91.623756
sha_transformbb_12, 2537708, 92.040721
sha_transformbb_3, 2547866, 92.234669
sha_transformbb_5, 2557877, 91.699716
sha_transformbb_7, 2567890, 91.518589
sha_transformbb_9, 2577900, 91.673337
sha_streambb_4, 2587904, 102.389867
sha_streambb_4, 2597906, 107.701716
sha_streambb_4, 2607908, 107.701716
sha_streambb_4, 2617910, 107.701716
sha_streambb_4, 2627912, 107.701716
sha_transformbb_17, 2637924, 92.056519
sha_transformbb_3, 2648193, 89.365058
sha_transformbb_5, 2658197, 89.171053
sha_transformbb_14, 2668211, 89.287533
sha_transformbb_17, 2678216, 89.276118
sha_transformbb_3, 2688549, 89.367862
sha_transformbb_5, 2698553, 89.171053
sha_transformbb_14, 2708567, 89.287533
sha_transformbb_17, 2718572, 89.276118
sha_transformbb_3, 2728905, 90.698749
sha_transformbb_5, 2738921, 91.722242
sha_transformbb_13, 2748932, 91.602253
sha_transformbb_9, 2758949, 91.666117
sha_transformbb_10, 2768954, 91.654479
sha_transformbb_11, 2778963, 91.675161
sha_transformbb_3, 2789587, 92.520722
sha_transformbb_5, 2799598, 91.699716
sha_transformbb_7, 2809630, 91.892095
sha_transformbb_14, 2819644, 91.684309
sha_transformbb_15, 2829645, 91.679666
sha_transformbb_11, 2839660, 91.588741
sha_transformbb_3, 2850380, 92.496517
sha_transformbb_5, 2860391, 91.699716
sha_transformbb_7, 2870407, 91.570339
sha_transformbb_9, 2880419, 91.671118
sha_transformbb_15, 2890431, 91.655879
sha_transformbb_11, 2900444, 91.590943
sha_transformbb_3, 2911132, 92.504537
sha_transformbb_5, 2921148, 91.722242
sha_transformbb_13, 2931166, 91.907413
sha_transformbb_14, 2941175, 91.675584
sha_transformbb_10, 2951176, 91.599790
sha_transformbb_11, 2961191, 91.668506
sha_transformbb_2, 2971193, 98.128204
sha_transformbb_3, 2981294, 86.222009
sha_transformbb_5, 2991305, 91.699716
sha_transformbb_13, 3001315, 91.521330
sha_transformbb_9, 3011328, 91.670551
sha_transformbb_10, 3021331, 91.654419
sha_transformbb_17, 3031340, 91.682669
sha_transformbb_2, 3041342, 98.163894
sha_transformbb_3, 3051443, 86.123537
sha_transformbb_5, 3061449, 91.677168
sha_transformbb_7, 3071528, 91.827525
sha_transformbb_9, 3081537, 91.571082
sha_transformbb_9, 3091546, 91.594351
sha_transformbb_15, 3101560, 91.685164
sha_transformbb_17, 3111569, 91.632434
sha_transformbb_3, 3121759, 92.547467
sha_transformbb_5, 3131765, 91.677168
sha_transformbb_13, 3141766, 91.572638
sha_transformbb_14, 3151770, 91.626041
sha_transformbb_16, 3161780, 91.592112
sha_transformbb_15, 3171793, 91.623723
sha_transformbb_11, 3181806, 91.620509
sha_transformbb_3, 3192006, 92.530024
sha_transformbb_5, 3202022, 91.722242
sha_transformbb_7, 3212035, 91.898802
sha_transformbb_14, 3222044, 91.634795
sha_streambb_4, 3232045, 101.941577
sha_streambb_4, 3242047, 107.701716
sha_streambb_4, 3252049, 107.701716
sha_streambb_4, 3262051, 107.701716
sha_streambb_4, 3272053, 108.150556
sha_transformbb_17, 3282063, 91.684059
sha_transformbb_3, 3292332, 89.365058
sha_transformbb_5, 3302336, 89.171053
sha_transformbb_14, 3312350, 89.287533
sha_transformbb_17, 3322355, 89.276118
sha_transformbb_3, 3332688, 89.367862
sha_transformbb_5, 3342692, 89.171053
sha_transformbb_14, 3352706, 89.287533
sha_transformbb_17, 3362711, 89.276118
sha_transformbb_3, 3373044, 90.698749
sha_transformbb_5, 3383060, 91.722242
sha_transformbb_13, 3393078, 91.907413
sha_transformbb_9, 3403091, 91.670551
sha_transformbb_10, 3413108, 91.625619
sha_transformbb_11, 3423121, 91.670723
sha_transformbb_3, 3433809, 92.504537
sha_transformbb_5, 3443815, 91.677168
sha_transformbb_7, 3453819, 91.569880
sha_transformbb_14, 3463830, 91.727880
sha_transformbb_15, 3473832, 91.679693
sha_transformbb_17, 3483841, 91.602856
sha_transformbb_3, 3494547, 92.465000
sha_transformbb_5, 3504563, 91.722242
sha_transformbb_13, 3514581, 91.907413
sha_transformbb_9, 3524594, 91.670551
sha_transformbb_15, 3534605, 91.655849
sha_transformbb_11, 3544620, 91.588741
sha_updatebb_6, 3554633, 91.549912
sha_transformbb_3, 3564737, 92.707069
sha_transformbb_5, 3574748, 91.699716
sha_transformbb_7, 3584764, 91.570339
sha_transformbb_14, 3594777, 91.725651
sha_transformbb_15, 3604780, 91.679720
sha_transformbb_17, 3614787, 91.605062
sha_transformbb_3, 3625475, 92.444871
sha_transformbb_5, 3635491, 91.722242
sha_transformbb_7, 3645504, 91.898802
sha_transformbb_14, 3655518, 91.684309
sha_transformbb_10, 3665528, 91.512308
sha_transformbb_10, 3675542, 91.623756
sha_updatebb_6, 3685589, 91.595935
sha_transformbb_3, 3695665, 92.767257
sha_transformbb_5, 3705681, 91.722242
sha_transformbb_7, 3715692, 91.547737
sha_transformbb_9, 3725704, 91.671118
sha_transformbb_10, 3735722, 91.625652
sha_transformbb_17, 3745729, 91.684890
sha_transformbb_3, 3756431, 92.416881
sha_transformbb_5, 3766437, 91.677168
sha_transformbb_7, 3776474, 91.914477
sha_transformbb_9, 3786487, 91.629778
sha_transformbb_10, 3796503, 91.625586
sha_transformbb_11, 3806517, 91.589301
sha_updatebb_6, 3816545, 91.600396
sha_transformbb_3, 3826649, 92.707069
sha_transformbb_5, 3836665, 91.722242
sha_transformbb_13, 3846676, 91.602253
sha_transformbb_9, 3856688, 91.616608
sha_transformbb_10, 3866706, 91.625652
sha_streambb_4, 3876710, 103.857164
sha_streambb_4, 3886712, 107.701716
sha_streambb_4, 3896714, 107.701716
sha_streambb_4, 3906716, 107.701716
sha_streambb_4, 3916718, 107.701716
sha_transformbb_3, 3927335, 90.614651
sha_transformbb_5, 3937339, 89.171053
sha_transformbb_14, 3947353, 89.287533
sha_transformbb_17, 3957358, 89.276118
sha_transformbb_3, 3967691, 89.367862
sha_transformbb_5, 3977695, 89.171053
sha_transformbb_14, 3987709, 89.287533
sha_transformbb_17, 3997714, 89.276118
sha_transformbb_3, 4008061, 89.343075
sha_transformbb_5, 4018065, 90.674686
sha_transformbb_13, 4028070, 91.627416
sha_transformbb_9, 4038076, 91.649871
sha_transformbb_15, 4048085, 91.685030
sha_transformbb_11, 4058094, 91.638240
sha_transformbb_3, 4068412, 92.575411
sha_transformbb_5, 4078428, 91.722242
sha_transformbb_13, 4088446, 91.907413
sha_transformbb_14, 4098455, 91.675584
sha_transformbb_10, 4108470, 91.571060
sha_transformbb_11, 4118485, 91.668506
sha_transformbb_3, 4129205, 92.496517
sha_transformbb_5, 4139221, 91.722242
sha_transformbb_7, 4149232, 91.547737
sha_transformbb_9, 4159244, 91.671118
sha_transformbb_10, 4169248, 91.654449
sha_transformbb_17, 4179255, 91.684890
sha_transformbb_3, 4189957, 92.416881
sha_transformbb_5, 4199973, 91.722242
sha_transformbb_7, 4209986, 91.898802
sha_transformbb_14, 4219995, 91.634795
sha_transformbb_10, 4230015, 91.620577
sha_transformbb_17, 4240026, 91.680448
sha_updatebb_6, 4250029, 91.566702
sha_transformbb_3, 4260119, 92.737121
sha_transformbb_5, 4270135, 91.722242
sha_transformbb_7, 4280146, 91.547737
sha_transformbb_9, 4290158, 91.671118
sha_transformbb_10, 4300162, 91.654449
sha_transformbb_17, 4310169, 91.684890
sha_transformbb_3, 4320913, 92.333346
sha_transformbb_5, 4330929, 91.722242
sha_transformbb_7, 4340942, 91.898802
sha_transformbb_14, 4350956, 91.684309
sha_transformbb_10, 4360957, 91.599790
sha_transformbb_11, 4370971, 91.589301
sha_updatebb_6, 4380985, 91.629129
sha_transformbb_3, 4391103, 92.677100
sha_transformbb_5, 4401114, 91.699716
sha_transformbb_13, 4411127, 91.573094
sha_transformbb_9, 4421137, 91.618816
sha_transformbb_10, 4431154, 91.625619
sha_transformbb_17, 4441163, 91.682669
sha_updatebb_6, 4451176, 91.486224
sha_transformbb_3, 4461294, 92.677100
sha_transformbb_5, 4471300, 91.677168
sha_transformbb_7, 4481351, 91.885413
sha_transformbb_14, 4491360, 91.634795
sha_transformbb_10, 4501361, 91.590595
sha_transformbb_18, 4511375, 91.696620
sha_streambb_4, 4521380, 104.050000
sha_streambb_4, 4531382, 107.701716
sha_streambb_4, 4541384, 107.701716
sha_streambb_4, 4551386, 107.701716
sha_streambb_4, 4561388, 108.150556
sha_transformbb_3, 4571397, 89.186194
sha_transformbb_5, 4581404, 89.157573
sha_transformbb_14, 4591418, 89.260582
sha_transformbb_17, 4601424, 89.274110
sha_transformbb_3, 4611789, 89.369252
sha_transformbb_5, 4621793, 89.171053
sha_transformbb_14, 4631807, 89.287533
sha_transformbb_17, 4641812, 89.276118
sha_transformbb_3, 4652159, 89.343075
sha_transformbb_5, 4662163, 90.674686
sha_transformbb_7, 4672178, 91.929879
sha_transformbb_9, 4682191, 91.628272
sha_transformbb_10, 4692198, 91.605148
sha_transformbb_17, 4702203, 91.673793
sha_transformbb_3, 4712621, 92.538177
sha_transformbb_5, 4722637, 91.722242
sha_transformbb_13, 4732648, 91.602253
sha_transformbb_9, 4742665, 91.666117
sha_transformbb_10, 4752670, 91.654479
sha_transformbb_11, 4762679, 91.675161
sha_transformbb_3, 4773345, 92.436167
sha_transformbb_5, 4783361, 91.722242
sha_transformbb_7, 4793374, 91.898802
sha_transformbb_14, 4803388, 91.684309
sha_transformbb_15, 4813389, 91.679666
sha_transformbb_11, 4823404, 91.588741
sha_updatebb_6, 4833417, 91.549912
sha_transformbb_3, 4843493, 92.767257
sha_transformbb_5, 4853504, 91.699716
sha_transformbb_7, 4863520, 91.570339
sha_transformbb_9, 4873532, 91.671118
sha_transformbb_10, 4883536, 91.654449
sha_transformbb_11, 4893547, 91.672942
sha_transformbb_3, 4904231, 92.456352
sha_transformbb_5, 4914237, 91.677168
sha_transformbb_7, 4924288, 91.885413
sha_transformbb_9, 4934301, 91.629778
sha_transformbb_10, 4944303, 91.654389
sha_transformbb_11, 4954318, 91.668506
sha_updatebb_6, 4964331, 91.549912
sha_transformbb_3, 4974407, 92.767257
sha_transformbb_5, 4984418, 91.699716
sha_transformbb_13, 4994431, 91.573094
sha_transformbb_14, 5004437, 91.623830
sha_transformbb_10, 5014452, 91.571060
sha_transformbb_11, 5024467, 91.668506
sha_transformbb_2, 5034469, 98.227652
sha_transformbb_3, 5044556, 86.144460
sha_transformbb_5, 5054562, 91.677168
sha_transformbb_7, 5064599, 91.914477
sha_transformbb_9, 5074612, 91.629778
sha_transformbb_10, 5084628, 91.625586
sha_transformbb_11, 5094642, 91.589301
sha_updatebb_6, 5104684, 91.571742
sha_transformbb_3, 5114774, 92.737121
sha_transformbb_5, 5124785, 91.699716
sha_transformbb_7, 5134798, 91.518589
sha_transformbb_9, 5144808, 91.673337
sha_transformbb_10, 5154825, 91.625619
sha_streambb_4, 5164827, 103.428919
sha_streambb_4, 5174829, 107.701716
sha_streambb_4, 5184831, 108.150556
sha_streambb_4, 5194833, 107.701716
sha_streambb_4, 5204835, 107.701716
sha_transformbb_3, 5215474, 90.619242
sha_transformbb_5, 5225478, 89.171053
sha_transformbb_14, 5235492, 89.287533
sha_transformbb_17, 5245497, 89.276118
sha_transformbb_3, 5255830, 89.367862
sha_transformbb_5, 5265834, 89.171053
sha_transformbb_14, 5275848, 89.287533
sha_transformbb_17, 5285853, 89.276118
sha_transformbb_3, 5296186, 89.367862
sha_transformbb_5, 5306190, 90.674686
sha_transformbb_7, 5316198, 91.624643
sha_transformbb_14, 5326202, 91.707236
sha_transformbb_15, 5336216, 91.680020
sha_transformbb_11, 5346223, 91.640453
sha_transformbb_3, 5356495, 92.613342
sha_transformbb_5, 5366506, 91.699716
sha_transformbb_7, 5376538, 91.892095
sha_transformbb_14, 5386552, 91.684309
sha_transformbb_15, 5396553, 91.679666
sha_transformbb_11, 5406554, 91.617496
sha_updatebb_6, 5416567, 91.549912
sha_transformbb_3, 5426643, 92.767257
sha_transformbb_5, 5436654, 91.699716
sha_transformbb_13, 5446667, 91.573094
sha_transformbb_9, 5456682, 91.668333
sha_transformbb_10, 5466700, 91.625652
sha_transformbb_17, 5476707, 91.684890
sha_transformbb_3, 5487395, 92.444871
sha_transformbb_5, 5497411, 91.722242
sha_transformbb_13, 5507429, 91.907413
sha_transformbb_9, 5517437, 91.621025
sha_transformbb_10, 5527453, 91.625586
sha_transformbb_11, 5537468, 91.668506
sha_transformbb_3, 5548188, 92.496517
sha_transformbb_5, 5558199, 91.699716
sha_transformbb_7, 5568215, 91.570339
sha_transformbb_9, 5578222, 91.621587
sha_transformbb_10, 5588225, 91.654419
sha_transformbb_11, 5598238, 91.670723
sha_transformbb_3, 5608940, 92.476468
sha_transformbb_5, 5618951, 91.699716
sha_transformbb_7, 5628983, 91.892095
sha_transformbb_9, 5638996, 91.629778
sha_transformbb_15, 5649006, 91.655819
sha_transformbb_18, 5659007, 91.636481
sha_updatebb_6, 5669054, 91.523311
sha_transformbb_3, 5679158, 92.707069
sha_transformbb_5, 5689174, 91.722242
sha_transformbb_13, 5699185, 91.602253
sha_transformbb_14, 5709198, 91.671146
sha_transformbb_10, 5719215, 91.571136
sha_transformbb_11, 5729226, 91.672942
sha_transformbb_3, 5739924, 92.428336
sha_transformbb_5, 5749930, 91.677168
sha_transformbb_7, 5759995, 91.856429
sha_transformbb_14, 5770009, 91.684309
sha_transformbb_10, 5780010, 91.599790
sha_transformbb_11, 5790025, 91.668506
sha_updatebb_7, 5800038, 91.543003
sha_streambb_4, 5810039, 105.648856
sha_streambb_4, 5820041, 107.701716
sha_streambb_4, 5830043, 107.701716
sha_streambb_4, 5840045, 107.701716
sha_transformbb_3, 5850338, 106.228937
sha_transformbb_5, 5860345, 89.001298
sha_transformbb_14, 5870355, 89.279644
sha_transformbb_15, 5880363, 89.288470
sha_transformbb_3, 5890792, 89.354371
sha_transformbb_5, 5900796, 89.171053
sha_transformbb_14, 5910810, 89.287533
sha_transformbb_17, 5920815, 89.276118
sha_transformbb_3, 5931148, 89.464124
sha_transformbb_5, 5941166, 89.046438
sha_transformbb_14, 5951170, 91.089291
sha_transformbb_15, 5961173, 91.679720
sha_transformbb_17, 5971184, 91.656846
sha_transformbb_3, 5981840, 92.452760
sha_transformbb_5, 5991856, 91.722242
sha_transformbb_13, 6001867, 91.602253
sha_transformbb_14, 6011875, 91.621620
sha_transformbb_15, 6021877, 91.679693
sha_transformbb_11, 6031890, 91.590943
sha_transformbb_3, 6042606, 92.448473
sha_transformbb_5, 6052622, 91.722242
sha_transformbb_13, 6062640, 91.907413
sha_transformbb_9, 6072653, 91.670551
sha_transformbb_10, 6082656, 91.654419
sha_transformbb_11, 6092665, 91.618955
sha_transformbb_3, 6103399, 92.468543
sha_transformbb_5, 6113405, 91.677168
sha_transformbb_13, 6123406, 91.572638
sha_transformbb_14, 6133415, 91.675584
sha_transformbb_10, 6143416, 91.599790
sha_transformbb_11, 6153431, 91.668506
sha_transformbb_3, 6164151, 92.496517
sha_transformbb_5, 6174162, 91.699716
sha_transformbb_7, 6184180, 91.921224
sha_transformbb_14, 6194189, 91.634795
sha_transformbb_10, 6204209, 91.620577
sha_transformbb_17, 6214220, 91.680448
sha_transformbb_12, 6224225, 91.925323
sha_transformbb_3, 6234369, 92.263909
sha_transformbb_5, 6244375, 91.677168
sha_transformbb_7, 6254379, 91.569880
sha_transformbb_14, 6264390, 91.727880
sha_transformbb_15, 6274400, 91.601298
sha_transformbb_17, 6284411, 91.600652
sha_updatebb_6, 6294442, 91.509427
sha_transformbb_3, 6304532, 92.737121
sha_transformbb_5, 6314543, 91.699716
sha_transformbb_7, 6324617, 91.805193
sha_transformbb_9, 6334626, 91.571082
sha_transformbb_16, 6344636, 91.655819
sha_transformbb_10, 6354655, 91.593519
sha_transformbb_11, 6364658, 91.598940
sha_transformbb_3, 6374848, 92.610049
sha_transformbb_5, 6384864, 91.722242
sha_transformbb_7, 6394875, 91.547737
sha_transformbb_14, 6404888, 91.725651
sha_transformbb_10, 6414899, 91.521537
sha_transformbb_11, 6424912, 91.670723
sha_transformbb_3, 6435628, 92.448473
sha_streambb_4, 6445630, 91.965380
sha_streambb_4, 6455636, 107.010070
sha_streambb_4, 6465638, 107.701716
sha_streambb_4, 6475640, 107.701716
sha_streambb_4, 6485642, 108.150556
sha_transformbb_5, 6495658, 104.106871
sha_transformbb_9, 6505666, 89.208987
sha_transformbb_11, 65156
\ No newline at end of file
instrument/examples/sha/instrumented_power/result.txt 0 → 100644
View file @ 0da352bb
06 Nov. 11:45 am
memAccessCycles = 4440193
pipelineCycles = 20502591
Statistics :
Total L1 Hits = 5406006
Total L2 Hits = 1928
Total L2 Misses = 14805
Total Prefetches = 9100
Mem Access Cycles = 4440193
L1 Data Cache
Hit Read = 2209850
Hit Writeback = 951041
Miss = 1928
L1 Instruction Cache
Hit Read = 3187056
Miss = 0
L2 Unified Cache
Hit Read = 1928
Hit Writeback = 12624
Inst. Miss = 24
Data Miss = 23881
Accesses = 4938338
L1 Hits = 0
L1 Miss = 0 (L1 Miss Rate = 0)
L2 Hits = 0
L2 Miss = 0 (L2 Miss Rate = 0)
instrument/examples/sieve/instrumented/erat_sieve_no_print_IR.c
View file @ 0da352bb
...@@ -27,7 +27,7 @@ struct test { ...@@ -27,7 +27,7 @@ struct test {
unsigned int v; unsigned int v;
unsigned int k; unsigned int k;
} m = { 1, 1 }; } m = { 1, 1 };
unsigned long m_addr = 0x7c8;
void sieve_func() { void sieve_func() {
int j_76; int j_76;
...@@ -41,7 +41,6 @@ void sieve_func() { ...@@ -41,7 +41,6 @@ void sieve_func() {
uintptr_t D_2240; uintptr_t D_2240;
uintptr_t D_2230; uintptr_t D_2230;
uintptr_t ivtmp_36; uintptr_t ivtmp_36;
unsigned long ivtmp_36_addr; // MANUAL
int j; int j;
int i; int i;
unsigned int sieve[500000]; unsigned int sieve[500000];
...@@ -216,7 +215,6 @@ memAccessCycles += simICache(0x31c, 12, &csim_result); ...@@ -216,7 +215,6 @@ memAccessCycles += simICache(0x31c, 12, &csim_result);
estimate_power("sieve_funcbb_13", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("sieve_funcbb_13", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 10 - (enterBlock(0xdd, 0xdf) ? 7 : 0); pipelineCycles += 10 - (enterBlock(0xdd, 0xdf) ? 7 : 0);
ivtmp_36 = (uintptr_t)&results; ivtmp_36 = (uintptr_t)&results;
ivtmp_36_addr = results_addr;
D_2230 = ivtmp_36 + 1999996; D_2230 = ivtmp_36 + 1999996;
// # SUCC: 14 [100.0%] (fallthru,exec) // # SUCC: 14 [100.0%] (fallthru,exec)
...@@ -227,7 +225,6 @@ memAccessCycles += simICache(0x328, 12, &csim_result); ...@@ -227,7 +225,6 @@ memAccessCycles += simICache(0x328, 12, &csim_result);
estimate_power("sieve_funcbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("sieve_funcbb_14", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
// TODO: UnmappedLS: Load GlobalVar results at line 224 // TODO: UnmappedLS: Load GlobalVar results at line 224
pipelineCycles += 8 - (enterBlock(0xe0, 0xe2) ? 7 : 0); pipelineCycles += 8 - (enterBlock(0xe0, 0xe2) ? 7 : 0);
memAccessCycles += simDCache(ivtmp_36_addr + 4, 1, &csim_result);
if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0) if (*(unsigned int*)((uintptr_t)ivtmp_36 + 4) == 0)
goto sieve_funcbb_16; goto sieve_funcbb_16;
else else
...@@ -241,7 +238,6 @@ memAccessCycles += simICache(0x334, 12, &csim_result); ...@@ -241,7 +238,6 @@ memAccessCycles += simICache(0x334, 12, &csim_result);
estimate_power("sieve_funcbb_15", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses)); estimate_power("sieve_funcbb_15", pipelineCycles, memAccessCycles, csim_result.L2Hits, (csim_result.prefetches + csim_result.L2Misses));
pipelineCycles += 9 - (enterBlock(0xe3, 0xe5) ? 7 : 0); pipelineCycles += 9 - (enterBlock(0xe3, 0xe5) ? 7 : 0);
ivtmp_36 = ivtmp_36 + 4; ivtmp_36 = ivtmp_36 + 4;
ivtmp_36_addr = ivtmp_36_addr + 4;
if (ivtmp_36 != D_2230) if (ivtmp_36 != D_2230)
goto sieve_funcbb_14; goto sieve_funcbb_14;
else else
......
instrument/examples/sieve/instrumented_power/power_trace.dat
View file @ 0da352bb
This source diff could not be displayed because it is too large. You can view the blob instead.
instrument/pipeline_sim.py
View file @ 0da352bb
...@@ -416,7 +416,7 @@ def annot_pipeline_sim(listISCFunctions, ...@@ -416,7 +416,7 @@ def annot_pipeline_sim(listISCFunctions,
# Block Done! # Block Done!
blockIndISC = blockObj.mapsTo[0] blockIndISC = blockObj.mapsTo[0]
blockISC = funcISC.cfg.listBlocks[blockIndISC] blockISC = funcISC.cfg.listBlocks[blockIndISC]
annot_str = "pipelineCycles += %d - (enterBlock(0x%x, 0x%x) ? 7 : 0);" % (currBlockCycles, annot_str = "pipelineCycles += %d - (enterBlock(0x%x, 0x%x) ? 5 : 0);" % (currBlockCycles,
blockObj.startLine, blockObj.startLine,
blockObj.endLine) blockObj.endLine)
annot = Annotation(annot_str, annot = Annotation(annot_str,
......
instrument/sha.sh
View file @ 0da352bb
#!/bin/sh #!/bin/sh
python instrument.py -i examples/sha/in_small.h -i examples/sha/ir2c.h -i examples/sha/my_defines.h -i examples/sha/my_mem.h -i examples/sha/my_mem_IR.c -i examples/sha/my_variable.h -i examples/sha/sha_driver_IR.c -i examples/sha/sha.h -i examples/sha/sha_IR.c -o examples/sha/sha_driver_IR.objdump -b examples/sha/sha_driver_IR.elf -p examples/sha/instrumented/ python instrument.py -i examples/sha/in_small.h -i examples/sha/ir2c.h -i examples/sha/my_defines.h -i examples/sha/my_mem.h -i examples/sha/my_mem_IR.c -i examples/sha/my_variable.h -i examples/sha/sha_driver_IR.c -i examples/sha/sha.h -i examples/sha/sha_IR.c -o examples/sha/sha_driver_IR.objdump -b examples/sha/sha_driver_IR.elf -p examples/sha/instrumented_power/
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